Senior Layout Engineer-DPG-LPDDR

Micron Technology
Hyderabad
Workplace: OnsiteFull timeFunction: Solutions Engineering & Sales EngineeringEducation: mastersSkills: ["Knowledge sharing","Continuous improvement"]

Own custom analog and mixed-signal layout for LPDDR PHYs, covering datapath, bias networks, IO analog frontends, and reference circuits. Deliver high-speed LPDDR interface layouts by tackling signal integrity challenges (skew control, impedance matching, shielding, crosstalk mitigation, jitter sensitivity). Build array-based layouts and custom digital block layouts, driving layout-aware co-building and closure through DRC/LVS, parasitic extraction, and simulation correlation to ensure first-silicon success and JEDEC compliance.

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FursaFursa
Micron Technology
Micron Technology
3 weeks ago

Senior Layout Engineer-DPG-LPDDR

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Source: Company careers pageValidated by: Fursa AI
Last checked: 15 hours agoStatus: Live

Job Summary

Own custom analog and mixed-signal layout for LPDDR PHYs, covering datapath, bias networks, IO analog frontends, and reference circuits. Deliver high-speed LPDDR interface layouts by tackling signal integrity challenges (skew control, impedance matching, shielding, crosstalk mitigation, jitter sensitivity). Build array-based layouts and custom digital block layouts, driving layout-aware co-building and closure through DRC/LVS, parasitic extraction, and simulation correlation to ensure first-silicon success and JEDEC compliance.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Job Function: Solutions Engineering & Sales Engineering
Seniority: Mid level

Key Responsibilities

  • •Own custom analog and mixed-signal layout for critical LPDDR PHY analog blocks, ensuring robustness across PVT, low noise coupling, and high matching accuracy.
  • •Complete high-speed LPDDR interface layout (LPDDRx) and handle signal integrity challenges such as skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity.
  • •Build and optimize array-based layouts for LPDDR DQ/DQS byte lanes, CA lanes, and replica paths with strict symmetry, pitch matching, repeatability, and scalability.
  • •Implement custom digital block layouts within the LPDDR PHY (training logic, calibration engines, test/debug circuitry) considering clocking, congestion, and interactions with analog regions.
  • •Drive layout-aware co-building with circuit designers to meet timing, noise, IR, and EM requirements; perform closure (DRC/LVS, parasitic extraction), support ECOs, and partner with silicon debug for first-silicon success.

Key Requirements

  • •B. Tech/B.E in Electronics, Electronics & Communications, or VLSI Engineering.
  • •M. Tech in Electronics Engineering, Microelectronics, or VLSI Engineering.
  • •Experience owning custom analog and mixed-signal layout for critical LPDDR PHY blocks (datapath, bias networks, IO analog frontends, reference circuits).
  • •Ability to complete high-speed LPDDR interface layout (LPDDRx) and address signal integrity challenges like skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity.
  • •Perform DRC/LVS closure, parasitic extraction reviews, and correlation with simulation results; support post-layout optimization/ECOs while maintaining JEDEC compliance.
Education:Master's in Electronics, Electronics & Communications, or VLSI Engineering
Skills:Knowledge sharingContinuous improvement
Tech Stack:LPDDRLPDDRxLPDDR PHYDRCLVSParasitic extractionSimulationECOJEDECVXL

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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