Customer Engagement Engineer II

Cadence Design Systems
San Jose
Workplace: OnsiteFull timeUSD 105,000 - 195,000 annuallyFunction: Customer Support (Service Desk)Experience: 1+ yearsEducation: bachelorsSkills: ["Communication","Debugging","Collaboration","Problem-solving"]

Support Cadence’s Palladium, Protium, and Virtual Protocol (PDAPP) products as part of the HSV Customer Support Team, working with customers, field AE teams, and R&D. Handle incoming SFDC cases, report tool bugs to R&D, help collect testcases, and test R&D fixes. Track customer metrics in JIRA and generate quality reports, while communicating complex technical issues clearly to customers and internal teams.

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Cadence Design Systems
Cadence Design Systems
1 day ago

Customer Engagement Engineer II

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Source: Company careers pageValidated by: Fursa AI
Last checked: 4 hours agoStatus: Live

Job Summary

Support Cadence’s Palladium, Protium, and Virtual Protocol (PDAPP) products as part of the HSV Customer Support Team, working with customers, field AE teams, and R&D. Handle incoming SFDC cases, report tool bugs to R&D, help collect testcases, and test R&D fixes. Track customer metrics in JIRA and generate quality reports, while communicating complex technical issues clearly to customers and internal teams.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Customer Support (Service Desk)
Seniority: Entry level

Key Responsibilities

  • •Handle incoming SFDC cases reported by field AEs and customers.
  • •Report tool bugs to R&D and work with field AEs and customers to gather necessary collaterals and/or testcases.
  • •Test R&D fixes/patches to validate customer-reported issues.
  • •Track customer metrics in JIRA and generate quality reports for management.
  • •Communicate complex technical issues clearly and concisely to internal teams and customers.
Travel: Low travel

Pay and Benefits

Salary: USD 105,000 - 195,000 annually
Equity and Bonus:Equity
Perks:Paid LeavePaid Holidays401kHealth InsuranceDental

Key Requirements

  • •BS in EE/CE with at least 1 year of experience in design and/or verification of complex digital designs, or in applications engineering/technical support.
  • •Strong knowledge of design/debug techniques and logic design.
  • •Knowledge of verification methodologies for complex EDA environments.
  • •Proficiency in HDL languages such as Verilog, SystemVerilog, and VHDL, with the ability to create test cases that reproduce customer issues.
  • •Proficiency with Unix/Linux scripting (ksh/bash/csh) and familiarity with emulation (Cadence Palladium preferred).
Experience:1+ years
Education:Bachelor's in EE/CE
Skills:CommunicationDebuggingCollaborationProblem-solving
Tech Stack:SFDCJIRAVerilogSystemVerilogVHDLUnixLinuxKshBashCshEmulationPalladiumTBASVASV coverageUPFUVMPCIeUSBEthernet

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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