Sr AMS Layout Engineer-DPG-LPDDR

Micron Technology
Hyderabad
Workplace: OnsiteFull timeFunction: Hardware, Embedded & Systems EngineeringExperience: 6+ yearsEducation: mastersSkills: ["Knowledge sharing","Continuous improvement","Data-driven optimization","Debugging","Collaboration"]

Own custom analog and mixed-signal layout for LPDDR PHY critical blocks, ensuring robustness across PVT while meeting low-noise, high-matching, and signal-integrity requirements. Execute high-speed LPDDR interface layouts addressing skew, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity. Design array-based and custom digital layout elements, perform DRC/LVS and parasitic extraction with simulation correlation, and support post-layout optimization/ECOs for JEDEC-compliant first-silicon success and high-volume manufacturability.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Micron Technology
Micron Technology
4 weeks ago

Sr AMS Layout Engineer-DPG-LPDDR

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 20 hours agoStatus: Live

Job Summary

Own custom analog and mixed-signal layout for LPDDR PHY critical blocks, ensuring robustness across PVT while meeting low-noise, high-matching, and signal-integrity requirements. Execute high-speed LPDDR interface layouts addressing skew, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity. Design array-based and custom digital layout elements, perform DRC/LVS and parasitic extraction with simulation correlation, and support post-layout optimization/ECOs for JEDEC-compliant first-silicon success and high-volume manufacturability.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Own the custom analog and mixed-signal layout of critical LPDDR PHY analog blocks, including datapath, bias networks, IO analog frontends, and reference circuits.
  • •Execute and optimize high-speed LPDDR interface layouts to address signal integrity challenges such as skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity.
  • •Design array-based layouts for LPDDR DQ/DQS byte lanes, CA lanes, and replica paths to ensure symmetry, pitch matching, repeatability, and scalability across configurations.
  • •Implement digital block layouts inside the LPDDR PHY (training logic, calibration engines, and test/debug circuitry) with careful handling of clocking, congestion, and analog sensitivity.
  • •Perform DRC/LVS, parasitic extraction and simulation correlation, then support post-layout optimization and ECOs to improve margin, yield, and manufacturability for first-silicon success.

Key Requirements

  • •6+ years of hands-on experience in analog and mixed-signal, high-speed serial links and layout.
  • •Experience designing and optimizing array-based layouts for LPDDR DQ/DQS byte lanes, CA lanes, and replica paths with strict symmetry and pitch matching.
  • •Ability to implement digital block layouts within LPDDR PHYs, including training logic, calibration engines, and test/debug circuitry.
  • •Strong knowledge of power distribution, grounding, isolation, and layout best practices (guard rings, deep-N-well, decoupling, and domain separation).
  • •Proficiency with DRC/LVS closure, parasitic extraction review, and silicon correlation; plus support for post-layout ECOs and margin/yield/manufacturability improvements while maintaining JEDEC compliance.
Experience:6+ yearsAnalog and mixed signalHigh-speed serial linksLPDDRSemiconductor design
Education:Master's in Electronics, Electronics & Communications, Microelectronics, or VLSI Engineering
Skills:Knowledge sharingContinuous improvementData-driven optimizationDebuggingCollaboration
Tech Stack:LPDDRAnalog and mixed-signal layoutHigh-speed serial linksSignal integritySkew controlImpedance matchingShieldingCrosstalk mitigationJitter sensitivityArray-based layoutsTraining logicCalibration enginesDRCLVSParasitic extractionSimulation correlationECOsJEDEC complianceAI/MLVXL-compatible layout flows

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
Glassdoor
Glassdoor: 3.7
WebsiteLinkedIn