ASIC Physical Design Engineer

NVIDIA
Taiwan
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 1+ yearsEducation: mastersSkills: ["Excellent English communication","Flow automation"]

Own ASIC physical design from RTL through timing signoff, including quality checks, synthesis, formal verification, partitioning, constraint and async checks, and hierarchical STA. Drive timing closure at partition and full-chip levels with special handling for IO and clock/test timing, then implement chip partitioning and floorplan. Build and enhance the end-to-end timing-closure flow (pre-layout to post-layout), including automation and methodology improvements.

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FursaFursa
NVIDIA
NVIDIA
2 hours ago

ASIC Physical Design Engineer

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Last checked: 2 hours agoStatus: Live

Job Summary

Own ASIC physical design from RTL through timing signoff, including quality checks, synthesis, formal verification, partitioning, constraint and async checks, and hierarchical STA. Drive timing closure at partition and full-chip levels with special handling for IO and clock/test timing, then implement chip partitioning and floorplan. Build and enhance the end-to-end timing-closure flow (pre-layout to post-layout), including automation and methodology improvements.
Location: Taiwan
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Perform STA for hierarchical design and timing budget creation.
  • •Create and validate constraints and conduct async checks.
  • •Drive timing closure for partition and full-chip levels, including IO, clock, and test timing.
  • •Handle synthesis, netlist quality checks, and formal verification.
  • •Implement chip partition and floorplan and develop/enhance timing-closure flow and flow automation (frontend to backend).

Key Requirements

  • •MS in EE, CS, or Microelectronics with 1+ year experience preferred.
  • •Project experience in IC design implementation.
  • •Coursework in circuit design and digital design.
  • •Hands-on experience with EDA tools such as Synopsys (FC/DC/PT/Formality) and/or Cadence (RC compiler/Genus/LEC).
  • •Proficiency with Python, perl, or TCL; good English reading and writing.
Experience:1+ yearsASICIC designPhysical designEDA
Education:Master's
Skills:Excellent English communicationFlow automation
Languages:English
Tech Stack:SynopsysFC/DCPTFormalityCadenceRC compilerGenusLECPythonPerlTCLSTATiming closureFormal Verification

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
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