RTL2GDS IC Sr. Principal Design Engineer

Cadence Design Systems
San Jose
Workplace: OnsiteFull timeUSD 161,000 - 299,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 10-12 yearsEducation: phdSkills: ["Customer interaction","Presentation skills","Analytical skills","Mentorship","Working in fast-paced environments"]

Provide technical pre-sales and post-sales support for Cadence Digital IC solutions at advanced nodes. You’ll help customers with digital implementation and signoff—synthesis, place & route, design closure, and STA/SDC debugging—through evaluations, presentations, and benchmarks. Collaborate with R&D to improve tools and methodologies, drive adoption of Cadence flows, and enhance or amend flows using Tcl/Perl/scripting, while mentoring junior engineers.

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Cadence Design Systems
Cadence Design Systems
3 days ago

RTL2GDS IC Sr. Principal Design Engineer

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Last checked: 3 hours agoStatus: Live

Job Summary

Provide technical pre-sales and post-sales support for Cadence Digital IC solutions at advanced nodes. You’ll help customers with digital implementation and signoff—synthesis, place & route, design closure, and STA/SDC debugging—through evaluations, presentations, and benchmarks. Collaborate with R&D to improve tools and methodologies, drive adoption of Cadence flows, and enhance or amend flows using Tcl/Perl/scripting, while mentoring junior engineers.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Provide technical support to customers for digital design implementation and signoff, including synthesis, place & route, design closure, and timing/power signoff.
  • •Guide customers in using Cadence technologies to meet design goals and project schedules.
  • •Deliver technical presentations, product demonstrations, and lead technical evaluations/benchmarks.
  • •Collaborate with R&D to enhance tools and methodologies to meet customer requirements.
  • •Drive adoption of Cadence tools and improve flows by amending/augmenting flows using Tcl and/or other programming skills, and capture best practices for future engagements.

Pay and Benefits

Salary: USD 161,000 - 299,000 annually
Equity and Bonus:Equity
Perks:Paid LeavePaid Holidays401k

Key Requirements

  • •BS, MS, or PhD in EE with 10-12 years industry experience in design and EDA (Digital Implementation/Signoff).
  • •Understand ASIC design implementation process and steps.
  • •Hands-on experience with Place & Route tools including Innovus, ICC2, and Fusion Compiler.
  • •Experience with Synthesis tools such as Genus, RTL Compiler, and Design Compiler.
  • •Strong STA and SDC debugging abilities, plus low-power analysis and 7/5nm node experience are a plus.
Experience:10-12 yearsEDAASIC designDigital implementationSemiconductor7/5nm
Education:PhD / Doctorate in EE
Skills:Customer interactionPresentation skillsAnalytical skillsMentorshipWorking in fast-paced environments
Tech Stack:TclPerlShell scriptingInnovusICC2Fusion CompilerGenusRTL CompilerDesign CompilerSTASDCSDC debugging7nm5nm

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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Glassdoor: 3.9
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