Substrate Packaging Defect Metro Tool Owner

Intel
Phoenix
Workplace: OnsiteFull timeUSD 103,730 - 198,820 annuallyFunction: Industrial, Process & Manufacturing EngineeringExperience: 3+ yearsEducation: bachelorsSkills: ["Independent work","Problem-solving","Leadership","Adaptability","Data communication"]

Drive defect metrology and yield improvement for Intel’s substrate packaging and panel-level assembly test manufacturing. You’ll use defect inspection tools to detect and resolve process issues, apply real-time data analysis and DOE summaries, and lead next-generation tool installation milestones from spec through qualification. Partner with factory and module teams to maintain WIP velocity, set up data flows to automation and yield systems, and present tool capabilities and insights to APTM leadership.

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FursaFursa
Intel
Intel
5 days ago

Substrate Packaging Defect Metro Tool Owner

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 13 hours agoStatus: Live
Reposted: similar role first listed 4 months ago

Job Summary

Drive defect metrology and yield improvement for Intel’s substrate packaging and panel-level assembly test manufacturing. You’ll use defect inspection tools to detect and resolve process issues, apply real-time data analysis and DOE summaries, and lead next-generation tool installation milestones from spec through qualification. Partner with factory and module teams to maintain WIP velocity, set up data flows to automation and yield systems, and present tool capabilities and insights to APTM leadership.
Location: Phoenix
Workplace: Onsite
Employment Type: Full time
Job Function: Industrial, Process & Manufacturing Engineering
Seniority: Mid level

Key Responsibilities

  • •Use defect inspection tools to detect and resolve process issues in collaboration with defect reduction, process integration, and module teams.
  • •Lead next-generation tool installation milestones from purchase-spec development through qualification with diverse stakeholders.
  • •Develop procedures and equipment setups for defect metrology tools to meet quality goals, including setting up data flows for new tools.
  • •Create equipment roadmaps and collaborate with equipment suppliers and supply chain partners to upgrade software/hardware for substrate packaging program needs.
  • •Perform statistical analysis and build visualizations/dashboards to communicate insights, including detecting data anomalies and corrections.

Pay and Benefits

Salary: USD 103,730 - 198,820 annually
Equity and Bonus:Equity
Perks:Health InsuranceRetirementPaid LeaveEquity

Key Requirements

  • •Bachelor’s degree in electrical engineering, chemical engineering, optical engineering, materials science, physics (or related) plus 3 years semiconductor experience, or a master’s with 2 years, or a PhD with 1+ year.
  • •Previous experience managing micro-contamination in semiconductor manufacturing.
  • •Experience as a yield analyst, defect reduction owner, and/or defect metrology tool ownership.
  • •Strong programming skills in Python.
  • •Knowledge of statistics and experimental design (DOE) for tool/process qualification and process development.
Experience:3+ yearsSemiconductor manufacturing
Education:Bachelor's in Electrical Engineering, Chemical Engineering, Optical Engineering, Materials Science, Physics (or related)
Skills:Independent workProblem-solvingLeadershipAdaptabilityData communication
Tech Stack:Python

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
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Glassdoor: 3.8
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