Design Engineer II

Cadence Design Systems
Nanjing
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 1+ yearsEducation: bachelorsSkills: ["Cross-functional communication","Collaboration","Independent work","Prioritization","Can-do attitude"]

Build and refine frontend RTL for high-performance physical IPs and contribute to advanced protocol PHY development. Work on feature/specification definition, low-power design concepts, synthesis/constraints/DFT basics, and RTL implementation for links such as USB4-PHY, PCIe, ONFI, eDP/DP, SATA, and more. Partner with digital verification and multiple engineering teams for FPGA/Palladium testing, pre/post-silicon application support, and global IP deliverables.

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Cadence Design Systems
Cadence Design Systems
2 hours ago

Design Engineer II

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Source: Company careers pageValidated by: Fursa AI
Last checked: 2 hours agoStatus: Live
Reposted: similar role first listed 7 months ago

Job Summary

Build and refine frontend RTL for high-performance physical IPs and contribute to advanced protocol PHY development. Work on feature/specification definition, low-power design concepts, synthesis/constraints/DFT basics, and RTL implementation for links such as USB4-PHY, PCIe, ONFI, eDP/DP, SATA, and more. Partner with digital verification and multiple engineering teams for FPGA/Palladium testing, pre/post-silicon application support, and global IP deliverables.
Location: Nanjing
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Contribute as a technical engineer in the IP frontend design team for high-performance consumer PHYs.
  • •Implement RTL and refine features/requirements throughout the design process.
  • •Apply knowledge of synthesis, constraint generation, power management, and DFT basics.
  • •Support low-power design features such as power islands, state retention, and isolation.
  • •Partner with digital verification and testing teams on coverage points, testing strategy, stimulus creation, and FPGA/Palladium testing; assist pre/post-silicon application support.

Key Requirements

  • •MS or BS in Electrical/Computer Engineering or a related degree.
  • •1+ years of relative industry working experience.
  • •Good knowledge of RTL design/verification best practices and ASIC end-to-end methodology.
  • •Knowledge of one or more industry serial standards (e.g., USB, DP, PCIe, Ethernet).
  • •Strong cross-functional communication skills in both English and Mandarin.
Experience:1+ years
Education:Bachelor's in Electrical/Computer Engineering
Skills:Cross-functional communicationCollaborationIndependent workPrioritizationCan-do attitude
Languages:EnglishMandarin
Tech Stack:RTLSystem VerilogPythonC/C++FPGAPalladiumUSBUSB4-PHYPCIeONFIEDP/DPSATAEthernetDFTLow-power designPower islandsState retentionIsolation

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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