Senior Principal Software Engineer

Cadence Design Systems
San Jose
Workplace: OnsiteFull timeUSD 161,000 - 299,000 annuallyFunction: Software EngineeringExperience: 5+ yearsSkills: ["Collaboration","Performance optimization","Technical excellence","Continuous learning","Rapid learning"]

Architect and evolve the Xcelium RTL/logic simulation engine, extending features and adding timing constraints verification capabilities. Tackle performance bottlenecks by designing, tuning, and innovating graph algorithms that support SDC constraints on massive graphs, improving compilation speed and memory usage. Partner with a distributed team to deliver RTL/logic simulation improvements, and write specifications and unit tests for C/C++ code.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Cadence Design Systems
Cadence Design Systems
10 hours ago

Senior Principal Software Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 10 hours agoStatus: Live

Job Summary

Architect and evolve the Xcelium RTL/logic simulation engine, extending features and adding timing constraints verification capabilities. Tackle performance bottlenecks by designing, tuning, and innovating graph algorithms that support SDC constraints on massive graphs, improving compilation speed and memory usage. Partner with a distributed team to deliver RTL/logic simulation improvements, and write specifications and unit tests for C/C++ code.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Software Engineering
Seniority: Mid level

Key Responsibilities

  • •Enhance and support the Xcelium RTL/logic simulator engine to add new features and extend existing features.
  • •Enhance and support Timing Constraints Verification technology used inside the Xcelium simulator.
  • •Design, tune, and innovate graph algorithms involving SDC constraints support on multi-billion-node graphs.
  • •Conduct deep-dive bottleneck analysis and implement performance optimizations in C/C++ to improve compilation speed and memory footprint.
  • •Collaborate with global team members and write specifications and unit tests for code.

Pay and Benefits

Salary: USD 161,000 - 299,000 annually
Equity and Bonus:Equity
Perks:Paid LeavePaid Holidays401kEquityHealth InsuranceDentalVision

Key Requirements

  • •MS in Computer Science or Electrical Engineering with at least 7 years of experience, or a PhD with at least 5 years of experience.
  • •5+ years of experience in EDA software development.
  • •Strong background in RTL/Logic Simulation, SDC constraints, and Timing Analysis (including path exceptions handling in a STA tool).
  • •Excellent programming skills in C/C++ with deep understanding of SystemVerilog or Verilog.
  • •Experience in multi-threaded/concurrent programming (prior RTL/logic simulation software development is a plus).
Experience:5+ yearsEDA software developmentSemiconductor technologyRTL/logic simulationTiming analysisSystemVerilog
Education:
Skills:CollaborationPerformance optimizationTechnical excellenceContinuous learningRapid learning
Tech Stack:CC++SystemVerilogVerilogSDCRTL/logic simulationGraph algorithmsMulti-threaded programmingSTA

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
Glassdoor
Glassdoor: 3.9
WebsiteLinkedInGlassdoor