Principal Product Engineer - Low Power Emulation

Cadence Design Systems
Shanghai
Full timeFunction: Energy & Utilities OperationsEducation: bachelorsSkills: ["Problem-solving","Debugging","Communication","Troubleshooting","Knowledge sharing"]

Drive low-power design and verification work, including UPF modeling, multi-voltage domain design, and power-aware simulation/emulation. Support customer projects across functional verification and power validation, and analyze/debug issues spanning power intent, RTL design, and system integration. Collaborate with global R&D teams to deliver optimized technical solutions, provide high-quality customer troubleshooting, and contribute to methodology development, knowledge sharing, and best-practice standardization.

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Cadence Design Systems
Cadence Design Systems
2 days ago

Principal Product Engineer - Low Power Emulation

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Last checked: 1 hour agoStatus: Live

Job Summary

Drive low-power design and verification work, including UPF modeling, multi-voltage domain design, and power-aware simulation/emulation. Support customer projects across functional verification and power validation, and analyze/debug issues spanning power intent, RTL design, and system integration. Collaborate with global R&D teams to deliver optimized technical solutions, provide high-quality customer troubleshooting, and contribute to methodology development, knowledge sharing, and best-practice standardization.
Location: Shanghai
Employment Type: Full time
Job Function: Energy & Utilities Operations
Seniority: Sr. Manager level

Key Responsibilities

  • •Drive low-power design and verification activities, including UPF modeling, multi-voltage domain design, and power-aware simulation/emulation.
  • •Support customer projects for functional verification and power validation.
  • •Analyze and debug complex issues related to power intent, RTL design, and system integration.
  • •Collaborate with global R&D teams to deliver and optimize technical solutions.
  • •Guide customers to success through technical support, troubleshooting, and contributions to methodology development and standardization.

Key Requirements

  • •Bachelor’s degree or above in Microelectronics, Electrical Engineering, or related fields.
  • •Experience in low-power design or verification (UPF/CPF/power-aware verification) and/or RTL design or verification (SystemVerilog/UVM preferred).
  • •Solid understanding of SoC architecture and digital design principles.
  • •Knowledge of power management techniques including power domains, isolation, retention, and DVFS.
  • •Strong problem-solving and debugging skills in complex systems; good English communication for a global environment.
Education:Bachelor's
Skills:Problem-solvingDebuggingCommunicationTroubleshootingKnowledge sharing
Languages:English
Tech Stack:UPFCPFSystemVerilogUVMRTLPower-aware simulationPower-aware emulationPalladiumProtiumEDA toolsSoC architectureASICMulti-voltage domain designPower intentDVFSPower domainsIsolationRetentionPower analysisEmulation platforms

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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Glassdoor: 3.9
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