Senior Reliability PDK and TFM engineer

Intel
Santa Clara, Phoenix
Workplace: HybridFull timeUSD 149,600 - 284,580 annuallyFunction: Solutions Engineering & Sales EngineeringEducation: bachelorsSkills: ["Written and verbal communication","Presentation skills","Attention to detail","Program management","Stakeholder management"]

Drive reliability design enablement for Intel Foundry technology nodes by defining and generating reliability PDK design rules, collateral, and QA/benchmarking analyses. Partner with internal teams and EDA vendors to enable competitive TFM tool/flow/methodology that supports design reliability verification. Lead competitive technology reliability benchmarking and plan delivery of PDKs, design rules, design collateral, TFM, and IP to enable customer design on Intel silicon and packaging technologies.

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Intel
Intel
3 days ago

Senior Reliability PDK and TFM engineer

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Last checked: 4 hours agoStatus: Live

Job Summary

Drive reliability design enablement for Intel Foundry technology nodes by defining and generating reliability PDK design rules, collateral, and QA/benchmarking analyses. Partner with internal teams and EDA vendors to enable competitive TFM tool/flow/methodology that supports design reliability verification. Lead competitive technology reliability benchmarking and plan delivery of PDKs, design rules, design collateral, TFM, and IP to enable customer design on Intel silicon and packaging technologies.
Location: Santa Clara, Phoenix
Workplace: Hybrid
Employment Type: Full time
Job Function: Solutions Engineering & Sales Engineering
Seniority: Mid level

Key Responsibilities

  • •Define and generate reliability-related PDK design rules and collateral covering reliability mechanisms, QA, and benchmarking analysis.
  • •Enable EDA tool and flow in synergy with PDK development, partnering with internal teams and EDA vendors to deliver competitive TFM for design reliability verification.
  • •Conduct competitive analysis and technology benchmarking for reliability and plan delivery of leading PDK, design rules, design collateral, TFM, and IP ecosystem to support internal and external customers.
  • •Support reliability design enablement for Intel Foundry strategy across leading technology nodes, including PDK, TFM, foundational IP, and DFR to achieve reliability co-optimization.
  • •Collaborate as a strong team player in a dynamic, diverse environment to meet program commitments on time.

Pay and Benefits

Salary: USD 149,600 - 284,580 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalRetirement

Key Requirements

  • •Bachelor’s degree in electrical engineering, physics, or related field with 6+ years relevant experience, or 4+ years with a master’s or PhD and 2+ years relevant experience.
  • •3+ years’ experience in PDK development, reliability tool and flow, or design-for-reliability reliability validation using PDK and EDA tool/flow development.
  • •Experience with PDK development and validation, including reliability design rules and their implementation in PDK and TFM.
  • •Experience with PDK and EDA tool/flow development and interaction with IP and SOC design validation/sign-off, including design impact and risk assessment.
  • •Knowledge of reliability verification and physics such as BTI, HCI, electromigration, high-voltage design, EOS, and ESD.
Experience:SemiconductorsEDAPDKReliability
Education:Bachelor's in electrical engineering, physics, or a related field
Skills:Written and verbal communicationPresentation skillsAttention to detailProgram managementStakeholder management
Tech Stack:PDKTFMEDAEDA toolTool/flow/methodologyAIScriptsAgentTechfile generationQuality assurance

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
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