ASIC Engineering Technical Leader || Physical Design | Floor Planning | GSP & PD | Exp - 11+ years

Cisco
Bengaluru, Hyderabad
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Experience: 13+ yearsEducation: bachelorsSkills: ["Debugging","Collaboration","Automation","Process improvement","Creative problem-solving"]

Drive the backend RTL-to-GDS physical design flow for next-generation networking ASICs, including hierarchical floorplanning, place & route, timing closure, power integrity, and physical verification. Analyze quality/efficiency gaps to evolve tools, flow, and methodology, collaborate with PD/RTL/DFT teams and EDA vendors, and improve CTS strategies. Own STA setup and ECO convergence, with strong debugging and automation using scripting (TCL/Shell/Perl/Python).

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FursaFursa
Cisco
Cisco
11 hours ago

ASIC Engineering Technical Leader || Physical Design | Floor Planning | GSP & PD | Exp - 11+ years

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Last checked: 11 hours agoStatus: Live

Job Summary

Drive the backend RTL-to-GDS physical design flow for next-generation networking ASICs, including hierarchical floorplanning, place & route, timing closure, power integrity, and physical verification. Analyze quality/efficiency gaps to evolve tools, flow, and methodology, collaborate with PD/RTL/DFT teams and EDA vendors, and improve CTS strategies. Own STA setup and ECO convergence, with strong debugging and automation using scripting (TCL/Shell/Perl/Python).
Location: Bengaluru, Hyderabad
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Lead RTL to GDS implementation for networking ASICs, covering hierarchical floorplanning, place & route, timing closure, power integrity, and physical verification/equivalence checks.
  • •Analyze physical design quality and efficiency gaps and propose incremental/evolutionary improvements to tools, flow, and methodology.
  • •Collaborate with physical design, RTL, DFT, tool/flow owners, and EDA vendors to improve physical design methodologies and CTS strategies.
  • •Develop and drive STA setup, convergence methodology, reviews, and sign-off for multi-mode multi-corner designs.
  • •Design and converge timing ECO implementation strategies using Tweaker/Primetime-based ECO flows, including STA-tool automation script development and debugging.

Key Requirements

  • •Bachelor’s or Master’s degree in Electrical or Computer Engineering.
  • •ASIC engineering experience with 13+ years of related work.
  • •Experience across ASIC physical implementation: floorplanning, clock/power distribution, global signal planning, I/O planning, and hard IP integration.
  • •Hands-on timing closure and physical convergence, including STA setup/convergence for multi-mode multi-corner designs.
  • •Good scripting skills (TCL/Shell/Perl/Python); TCL/Perl required, Python a plus.
Experience:13+ yearsASICEDASub 16/14/7/5/3nm
Education:Bachelor's in Electrical or Computer Engineering
Skills:DebuggingCollaborationAutomationProcess improvementCreative problem-solving
Tech Stack:RTLGDSTCLShellPerlPythonCadence InnovusSynopsys ICC2Synopsys DCSynopsys FCSynopsys FormalityCadence LECPrimetime-DMSAApache RedhawkSynopsys ICVMentor CalibreMulti-modeMulti-cornerStatic Timing VerificationEquivalence checks

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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