Technical Leader DFT & STA

Cisco
Armenia
Workplace: OnsiteFull timeFunction: Administration & Executive AssistanceExperience: 8+ yearsEducation: bachelorsSkills: ["Detail-oriented","Analytical thinking","Communication","Team collaboration","Problem solving"]

Join Cisco’s Silicon One team to define physical design methodologies and develop robust flows for advanced ASICs. You’ll lead DFT and Static Timing Analysis (STA) work by creating and validating timing constraints across block and full-chip test modes, checking timing for exceptions, and developing SDC/CDC checks. Partner with cross-functional teams to streamline STA execution, debug timing/flow issues, and improve accuracy and progress for complex chip partitions.

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FursaFursa
Cisco
Cisco
6 months ago

Technical Leader DFT & STA

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Job Summary

Join Cisco’s Silicon One team to define physical design methodologies and develop robust flows for advanced ASICs. You’ll lead DFT and Static Timing Analysis (STA) work by creating and validating timing constraints across block and full-chip test modes, checking timing for exceptions, and developing SDC/CDC checks. Partner with cross-functional teams to streamline STA execution, debug timing/flow issues, and improve accuracy and progress for complex chip partitions.
Location: Armenia
Workplace: Onsite
Employment Type: Full time
Job Function: Administration & Executive Assistance

Key Responsibilities

  • •Develop timing constraints at block, sub-chip, and full-chip levels for test modes, including quality checks like duplicated constraints and SDC promotion/demotion between block and top-level.
  • •Check timing for unconstrained endpoints and cases such as no-clock conditions.
  • •Perform or support SDC validation, CDC delay checks, and SDC flow development as needed.
  • •Develop methodologies, guidelines, and checklists to streamline STA work and resolve design/flow issues to ensure accurate progress.

Key Requirements

  • •Bachelor’s degree in electrical or computer engineering (or equivalent) with 8+ years of related work experience.
  • •Experience developing block/full-chip SDCs for test modes such as scan shift, scan capture, and ATPG capture modes.
  • •Expertise in Static Timing Analysis with hands-on use of STA tools like PrimeTime.
  • •Programming skills in at least two of: Perl, TCL, Python, Makefile (or similar scripting languages).
  • •Strong background in debugging/analyzing timing constraints and timing closure for DFT modes (scan shift/capture and BIST).
Experience:8+ yearsASIC designDFTStatic Timing AnalysisSemiconductor designPhysical designHardware verification
Education:Bachelor's in Electrical or computer engineering
Skills:Detail-orientedAnalytical thinkingCommunicationTeam collaborationProblem solving
Tech Stack:ASICPhysical DesignDFTSTAStatic Timing AnalysisTiming constraintsClock groupsClock exclusivitySDCSDC validationCDC delay checkSDC flow developmentUnconstrained endpointsPrimeTimePerlTCLPythonMakefileScan shiftScan capture

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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