SoC Digital Design Engineer, Multimedia Lab

TikTok
San Jose
Workplace: OnsiteFull timeFunction: Creative Production (Video/Audio/Photo)Experience: 1+ yearsEducation: bachelorsSkills: ["Technical excellence","Cross-functional collaboration","Attention to design robustness"]

Build scalable video codec SoC hardware for advanced video encoding and processing, contributing to early architecture definition (NoC/CPU/NPU/ISP/Codec) and PPA evaluation. Implement RTL in Verilog/SystemVerilog, run lint and CDC/RDC checks, and support low-power design using clock/power gating and UPF. Collaborate across verification and backend/mid-end teams for synthesis, SDC generation, static timing analysis, coverage closure, and power optimization.

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FursaFursa
TikTok
TikTok
1 month ago

SoC Digital Design Engineer, Multimedia Lab

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Last checked: 17 hours agoStatus: Live

Job Summary

Build scalable video codec SoC hardware for advanced video encoding and processing, contributing to early architecture definition (NoC/CPU/NPU/ISP/Codec) and PPA evaluation. Implement RTL in Verilog/SystemVerilog, run lint and CDC/RDC checks, and support low-power design using clock/power gating and UPF. Collaborate across verification and backend/mid-end teams for synthesis, SDC generation, static timing analysis, coverage closure, and power optimization.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Creative Production (Video/Audio/Photo)
Seniority: Entry level

Key Responsibilities

  • •Participate in defining SoC top or subsystem architecture (NoC/CPU/NPU/ISP/Codec) and conduct PPA evaluation during early design.
  • •Write high-quality, well-structured RTL code in Verilog/SystemVerilog and maintain related design documentation.
  • •Perform lint, CDC, and RDC checks to ensure code standard compliance and design robustness.
  • •Collaborate with verification for debugging and coverage closure; support synthesis, SDC generation, STA, and power optimization with backend/mid-end teams.
  • •Contribute to chip low-power strategy, applying clock gating and power gating techniques and supporting the UPF flow.

Key Requirements

  • •Bachelor's degree or higher in Microelectronics, Integrated Circuits, Computer Science, Electrical Engineering, or a related field.
  • •1+ years of experience in digital front-end design (open to candidates with less experience).
  • •Mastery of Verilog/SystemVerilog with a solid foundation in digital circuits.
  • •Proficiency with mainstream front-end EDA tools (e.g., Spyglass, Design Compiler, PrimeTime).
  • •Fluency in at least one scripting language (Python, Perl, Tcl, Makefile) for workflow automation.
Experience:1+ years
Education:Bachelor's in Microelectronics, Integrated Circuits, Computer Science, Electrical Engineering, or a related field
Skills:Technical excellenceCross-functional collaborationAttention to design robustness
Tech Stack:FPGAASICSoCVideo codecHardware acceleratorsNoCCPUNPUISPCodecRTLVerilogSystemVerilogPPA (Power, Performance, Area)LintCDC (Clock Domain Crossing)RDC (Reset Domain Crossing)SynthesisSDC (Synopsys Design Constraints)STA (Static Timing Analysis)

Company Brief

TikTok
Short-form video platform that lets users create, share, and discover entertainment content through algorithmic recommendations. It also offers advertising and creator tools for brands, influencers, and businesses.
Industry: Digital Media
Company Size: Enterprise (1,001+ employees)
Growth: Scaleup
Headquarters: Singapore, Singapore
Founded: 2016
WebsiteLinkedIn