IC Design Engineer

Broadcom
San Jose
Full timeUSD 143,800 - 230,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 12+ yearsEducation: bachelorsSkills: ["Troubleshooting","Continuous improvement","Problem-solving"]

Own top-level DFT planning and integration for multi-power-domain IC designs. You’ll manage ATPG and ATE interfaces, including ATE bring-up and failure analysis, while driving test time reduction. The role also covers synthesis, formal verification, and performing STA and simulation for DFT modes. Troubleshoot DFT issues and continuously improve the DFT flow to increase reliability and manufacturability.

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FursaFursa
Broadcom
Broadcom
1 month ago

IC Design Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 6 days agoStatus: Live
Reposted: similar role first listed 6 months ago

Job Summary

Own top-level DFT planning and integration for multi-power-domain IC designs. You’ll manage ATPG and ATE interfaces, including ATE bring-up and failure analysis, while driving test time reduction. The role also covers synthesis, formal verification, and performing STA and simulation for DFT modes. Troubleshoot DFT issues and continuously improve the DFT flow to increase reliability and manufacturability.
Location: San Jose
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Director level

Key Responsibilities

  • •Lead top-level DFT planning and integration for multi-power-domain designs.
  • •Manage the ATPG and ATE interfaces, including ATE bring-up and failure analysis.
  • •Drive test time reduction strategies.
  • •Handle synthesis, formal verification, and STA and simulation for DFT modes.
  • •Troubleshoot DFT-related issues and continuously improve the DFT flow.

Pay and Benefits

Salary: USD 143,800 - 230,000 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalVision401kEsppEmployee AssistancePaid HolidaysPaid LeaveParental Leave

Key Requirements

  • •Extensive experience with Siemens Tessent tool suite.
  • •Bachelors degree with 12+ years of related experience (or Masters degree with 10+ years).
  • •Responsible for top-level DFT planning and integration.
  • •Manage ATPG and ATE interfaces, including ATE bring-up and failure analysis.
  • •Perform synthesis, formal verification, and STA and simulation for DFT modes.
Experience:12+ yearsIC designDFTSemiconductor testing
Education:Bachelor's
Skills:TroubleshootingContinuous improvementProblem-solving
Tech Stack:Siemens TessentDFTATPGATESynthesisFormal verificationSTAStatic Timing AnalysisSimulationMulti-power domain

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn