PLL Design/ Integration Staff Engineer - Adaptive Computing Group

AMD
San Jose
Workplace: HybridFull timeUSD 145,600 - 208,000 annuallyFunction: Design (Product/UX/UI/Visual)Education: mastersSkills: ["Collaboration","Communication","Analytical thinking","Problem-solving","Initiative"]

Lead the design, integration, and characterization of Phase-Locked Loops (PLLs) for FPGA products across advanced process nodes. Work within AMD’s AECG Fabric and global Clock/PLL team to architect analog/mixed-signal PLL building blocks, integrate PLL topologies to meet jitter/power/area goals, and drive lab bring-up and performance characterization. Contribute to system-level simulations and validate PLL IP integration in the FPGA environment using Vivado and related flows.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
AMD
AMD
1 month ago

PLL Design/ Integration Staff Engineer - Adaptive Computing Group

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 5 hours agoStatus: Live

Job Summary

Lead the design, integration, and characterization of Phase-Locked Loops (PLLs) for FPGA products across advanced process nodes. Work within AMD’s AECG Fabric and global Clock/PLL team to architect analog/mixed-signal PLL building blocks, integrate PLL topologies to meet jitter/power/area goals, and drive lab bring-up and performance characterization. Contribute to system-level simulations and validate PLL IP integration in the FPGA environment using Vivado and related flows.
Location: San Jose
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Architect and integrate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, loop filters), LDO, phase interpolator, and high-speed divider into FPGA products across advanced process nodes.
  • •Lead integration of different PLL topologies (integer-N, fractional-N, all-digital/ADPLL) to meet power, area, jitter, and frequency specifications at the product level.
  • •Address advanced-node challenges including self-heating, electromigration, VCO linearization, and device-level noise optimization for product-level jitter.
  • •Supervise and verify PD-produced layouts to ensure floorplanning, matching, and parasitic minimization.
  • •Own PLL bring-up in the lab, performing performance characterization and conducting system-level simulations/validation for PLL IP integration in the FPGA environment using Vivado or similar tools/flows.

Pay and Benefits

Salary: USD 145,600 - 208,000 annually

Key Requirements

  • •Solid foundation in IC design and manufacturing, including analog/digital IP integration (e.g., PLLs, LDOs, Phase Interpolators), chip design, silicon processes, and packaging technologies.
  • •Strong understanding of device physics, reliability, and silicon chip manufacturing.
  • •Experience with post-silicon validation and characterization for modern adaptive computing architectures.
  • •Background in digital design/verification and SystemVerilog modeling.
  • •System-level simulation and validation experience for PLL IP integration in an FPGA environment (e.g., using Vivado or similar tools/flows).
Experience:Adaptive computingIC designFPGASemiconductors
Education:Master's in electrical & electronics engineering
Skills:CollaborationCommunicationAnalytical thinkingProblem-solvingInitiative
Languages:En-us
Tech Stack:Phase-Locked LoopsPLLsFPGAVCOCharge pumpsDividersPFDsLoop filtersLDOPhase InterpolatorHigh Speed DividerInteger-NFractional-NADPLLSystemVerilogVivadoClock synthesisClock recoveryDLLCDR

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
WebsiteLinkedIn