PLL Design/ Integration Staff Engineer - Adaptive Computing Group

Lead the design, integration, and characterization of Phase-Locked Loops (PLLs) for FPGA products across advanced process nodes. Work within AMD’s AECG Fabric and global Clock/PLL team to architect analog/mixed-signal PLL building blocks, integrate PLL topologies to meet jitter/power/area goals, and drive lab bring-up and performance characterization. Contribute to system-level simulations and validate PLL IP integration in the FPGA environment using Vivado and related flows.