Senior DFT Engineer

NVIDIA
United States
Workplace: OnsiteFull timeUSD 136,000 - 264,500 annuallyFunction: Solutions Engineering & Sales EngineeringExperience: 5+ yearsEducation: mastersSkills: ["Analytical skills","Cross-functional communication","Mentoring","Programming aptitude","Written communication"]

Lead silicon test innovation by designing and deploying advanced DFT test methodologies across NVIDIA’s next-generation platforms. Partner with VLSI and Product Engineering to implement test access mechanisms, IO/memory BIST, and scan compression. Own end-to-end chip bring-up planning from pre-silicon to production, develop reusable bring-up playbooks, and guide junior engineers to improve quality and efficiency.

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FursaFursa
NVIDIA
NVIDIA
2 months ago

Senior DFT Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 16 hours agoStatus: Live
Reposted: similar role first listed 7 months ago

Job Summary

Lead silicon test innovation by designing and deploying advanced DFT test methodologies across NVIDIA’s next-generation platforms. Partner with VLSI and Product Engineering to implement test access mechanisms, IO/memory BIST, and scan compression. Own end-to-end chip bring-up planning from pre-silicon to production, develop reusable bring-up playbooks, and guide junior engineers to improve quality and efficiency.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Solutions Engineering & Sales Engineering
Seniority: Mid level

Key Responsibilities

  • •Design and roll out advanced test methodologies on NVIDIA’s next-generation silicon platforms.
  • •Implement test access mechanisms, IO BIST, memory BIST, and scan compression with cross-functional partners.
  • •Collaborate with VLSI and Product Engineering to design innovative DFT approaches.
  • •Lead end-to-end planning and execution of new chip bring-up from pre-silicon through production deployment.
  • •Develop and standardize silicon bring-up methodologies, processes, and reusable checklists/playbooks, and mentor junior engineers.

Pay and Benefits

Salary: USD 136,000 - 264,500 annually
Equity and Bonus:Equity

Key Requirements

  • •BSEE (or equivalent) with 5+ years, MSEE with 3+ years, or PhD in DFT or related domains.
  • •Expertise defining scan test plans, BIST (memories and IOs), fault modeling, ATPG, and fault simulation.
  • •Strong analytical skills for verification/validation of test patterns and logic on complex multi-million gate builds using vendor tools.
  • •Experience in silicon debug and bring-up, including pattern formats, failure processing, and test program development.
  • •Strong programming and scripting skills, plus excellent written and oral communication.
Experience:5+ yearsSemiconductorVLSISoCSilicon bring-upSilicon test
Education:Master's in DFT or related domains (BSEE/MSEE/PhD)
Skills:Analytical skillsCross-functional communicationMentoringProgramming aptitudeWritten communication

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
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