Director, Physical Design

Lead physical design execution for advanced SoC/ASIC programs, owning PPA optimization across floor-plans, area, and interconnects to hit stringent power, performance, and area targets. Drive implementation across advanced process nodes while managing a team spanning physical design, circuit design, DFT, and integration. Partner with global RTL, NPI, packaging, and architecture teams, oversee automation infrastructure, and conduct deep design reviews including EMIR analysis and timing signoff closure.