Senior Silicon Design Engineer - DFT

AMD
Singapore
Workplace: HybridFull timeSGD 67,900 - 97,000 annuallyFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Communication","Teamwork","Analytical thinking","Problem-solving","Cross-site collaboration"]

Own the generation, validation, and delivery of scan test patterns for next-generation SERDES IPs and SoCs, partnering with product test teams to debug pattern, model, and netlist issues. Improve scan architecture and coverage, perform ATPG and gate-level netlist analysis to resolve testability gaps, and collaborate with physical design engineers on closure. Address DFT needs for high-frequency PHY IP designs while minimizing performance impact across globally distributed teams.

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FursaFursa
AMD
AMD
22 hours ago

Senior Silicon Design Engineer - DFT

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 13 hours agoStatus: Live

Job Summary

Own the generation, validation, and delivery of scan test patterns for next-generation SERDES IPs and SoCs, partnering with product test teams to debug pattern, model, and netlist issues. Improve scan architecture and coverage, perform ATPG and gate-level netlist analysis to resolve testability gaps, and collaborate with physical design engineers on closure. Address DFT needs for high-frequency PHY IP designs while minimizing performance impact across globally distributed teams.
Location: Singapore
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Own the generation, validation, and delivery of scan test patterns for next-generation SERDES IPs and SoCs.
  • •Partner with product test teams to troubleshoot pattern, model, and netlist issues during test bring-up.
  • •Improve scan architecture, scan coverage, test models, execution methods, and overall product quality.
  • •Perform ATPG pattern and gate-level netlist analysis to identify and resolve testability and coverage issues.
  • •Collaborate with physical design engineers on design closure using static timing, clock-domain crossing, netlist, and power analysis; address DFT requirements for high-frequency PHY IP designs.

Pay and Benefits

Salary: SGD 67,900 - 97,000 annually

Key Requirements

  • •Experience with design-for-test methodologies, including scan test and automatic test pattern generation (ATPG), particularly with Tessent flows.
  • •Strong knowledge of industry-standard ATPG tools and their use for pattern generation, fault coverage, and test quality.
  • •Ability to debug ATPG patterns, scan structures, test models, and gate-level netlists.
  • •Understanding of IEEE 1149.1 boundary scan, IEEE 1500 embedded core test, and memory BIST concepts.
  • •Bachelors or Masters degree in computer engineering or electrical engineering.
Education:Bachelor's in computer engineering / electrical engineering
Skills:CommunicationTeamworkAnalytical thinkingProblem-solvingCross-site collaboration
Languages:En-us
Tech Stack:DFTScan test patternsSERDESSoCsATPGTessentFault coverageIEEE 1149.1IEEE 1500Memory BISTMulti-clock designsMulti-power-domain designsStatic timing analysisClock-domain crossingStatic power analysisNetlistPHY IPBoundary scanEmbedded core testGate-level netlist analysis

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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