SOC Engineer

AMD
Markham
Workplace: HybridFull timeCAD 124,800 - 187,200 annuallyFunction: Software EngineeringEducation: bachelorsSkills: ["Communication","Problem-solving","Analytical thinking","Cross-functional collaboration","Initiative"]

Own SOC design and integration for advanced silicon on AMD’s SOC design team. Integrate AMD and third-party IP and key subsystem elements (fabric, voltage/clock crossings, clocks, resets, fuses, and I/O), develop Verilog RTL, and guide decisions impacting top-level latency and performance. Partner across IP development, verification, front-end integration, and physical design teams, performing SOC power ownership and static verification (RTL, CDC, Power, Connectivity).

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FursaFursa
AMD
AMD
1 day ago

SOC Engineer

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Last checked: 8 hours agoStatus: Live

Job Summary

Own SOC design and integration for advanced silicon on AMD’s SOC design team. Integrate AMD and third-party IP and key subsystem elements (fabric, voltage/clock crossings, clocks, resets, fuses, and I/O), develop Verilog RTL, and guide decisions impacting top-level latency and performance. Partner across IP development, verification, front-end integration, and physical design teams, performing SOC power ownership and static verification (RTL, CDC, Power, Connectivity).
Location: Markham
Workplace: Hybrid
Employment Type: Full time
Job Function: Software Engineering

Key Responsibilities

  • •Drive SOC-level design and integration across the chip system.
  • •Integrate IP and SOC-level fabric, including voltage and clock crossings, clocks, resets, fuses, and I/O.
  • •Develop RTL design and coding for various SOC sections and related logic.
  • •Own SOC power design and perform static verification (RTL, CDC, Power, Connectivity).
  • •Lead one of the specified SOC domains while partnering with verification, front-end integration, and physical design teams.

Pay and Benefits

Salary: CAD 124,800 - 187,200 annually

Key Requirements

  • •Own SOC-level integration efforts across IP, verification, front-end integration, and physical design teams.
  • •Verilog RTL development in a CPU/SOC/ASIC environment.
  • •Experience with SOC integration/architecture and system bus protocols such as AXI or PCIe.
  • •Background in power implementation methodology and UPF, plus static timing analysis.
  • •Familiarity with static verification (RTL, CDC, Power, Connectivity) and collaboration with physical design teams; scripting skills (Ruby, Perl, Shell, TCL) are a plus.
Education:Bachelor's in ECE/EEE
Skills:CommunicationProblem-solvingAnalytical thinkingCross-functional collaborationInitiative
Languages:English
Tech Stack:SOCSOC designIntegrationVerilogRTLCDCUPFStatic timing analysisStatic verificationAXIPCIeRubyPerlShellTCLStatic timing

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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