Design Engineering Architect — Memory Modeling Portfolio

Cadence Design Systems
Seoul
Workplace: OnsiteFull timeFunction: Solutions Engineering & Sales EngineeringExperience: 16+ yearsEducation: mastersSkills: ["Communication","Teamwork","Problem-solving"]

Architect Cadence’s Virtual Solutions R&D features for Accelerated Verification IP, enabling hardware/software co-development with Palladium/Protium emulators. Work on RTL/C++ feature implementation, write tests, review code, and coordinate with cross-functional teams to deliver high-quality verification solutions across hyperscale AI computing, mobile, automotive, and defense/aerospace industries.

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Cadence Design Systems
Cadence Design Systems
4 months ago

Design Engineering Architect — Memory Modeling Portfolio

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Source: Company careers pageValidated by: Fursa AI
Last checked: 8 hours agoStatus: Live

Job Summary

Architect Cadence’s Virtual Solutions R&D features for Accelerated Verification IP, enabling hardware/software co-development with Palladium/Protium emulators. Work on RTL/C++ feature implementation, write tests, review code, and coordinate with cross-functional teams to deliver high-quality verification solutions across hyperscale AI computing, mobile, automotive, and defense/aerospace industries.
Location: Seoul
Workplace: Onsite
Employment Type: Full time
Job Function: Solutions Engineering & Sales Engineering

Key Responsibilities

  • •Analyze incoming customer requirements, map to product feature enhancements and present proposed solutions for review and agreement within the R&D team.
  • •Implement product features using latest RTL and C++ language standards within a significant existing product code base.
  • •Write unit and feature tests for features that you have developed.
  • •Review implementation approaches and code developed by other team members.
  • •Work within a larger cross-functional team to ensure quality and timely deliveries and deployments of product features to customers.
  • •Architect the Performance verification solution and deploy across worldwide customer base

Key Requirements

  • •Bachelor’s Degree with 16+ years of experience or Master’s with 14+ years of experience or PhD with 10+ years of experience.
  • •Strong English verbal and written communications skills.
  • •Strong software engineering and development skills in C/C++ including modern source code control environments.
  • •Experience developing software related to or using hardware communication protocols like AMBA (CHI, AXI, ACE) or GUI framework tools, or related hardware protocols.
  • •Experience with SystemVerilog HDL is preferred and experience with simulation and/or emulation technology is preferred.
Experience:16+ yearsElectronicsHardware emulationAI computingHyperscaleMobileAutomotiveDefense/aerospace
Education:Master's
Skills:CommunicationTeamworkProblem-solving
Languages:English
Tech Stack:C++CSystemVerilogRTLAMBAGit

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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Glassdoor: 3.9
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