Sr Principal Design Engineer

Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 12-14 yearsEducation: mastersSkills: ["Verilog","HVL","UVM","OVM","Specman e","ERM","Assertions","Constraint randomization","Formal verification","Testbench","RTL","GLS","SDF","Perl","Tcl","Automation"]

Senior hardware design and verification engineer responsible for delivering VLSI verification environments and RTL blocks. Drives Verilog/HVL-based testbenches with UVM/OVM/eRM methodologies, develops assertions, constraints, and coverage, and collaborates on project schedules. Requires strong RTL/GLS debugging skills, scripting in Perl/Tcl, and independent delivery of complex verification tasks in a fast-paced semiconductor environment.

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Cadence Design Systems
Cadence Design Systems
6 months ago

Sr Principal Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 7 hours agoStatus: Live
Reposted: similar role first listed 9 months ago

Job Summary

Senior hardware design and verification engineer responsible for delivering VLSI verification environments and RTL blocks. Drives Verilog/HVL-based testbenches with UVM/OVM/eRM methodologies, develops assertions, constraints, and coverage, and collaborates on project schedules. Requires strong RTL/GLS debugging skills, scripting in Perl/Tcl, and independent delivery of complex verification tasks in a fast-paced semiconductor environment.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Lead the design and verification of RTL blocks and verification environments for VLSI projects.
  • •Develop and maintain testbenches using UVM/OVM/eRM methodologies and improve coverage metrics.
  • •Create and close assertions, implement constraint randomization, and debug GLS/RTL simulations.
  • •Automate verification tasks with Perl/Tcl scripting and improve flow efficiency.
  • •Collaborate with project teams to plan schedules and ensure on-time delivery of verification milestones.

Key Requirements

  • •12-14 years of work experience in the VLSI domain with a master’s or bachelor’s degree in engineering
  • •Strong expertise in Verilog and HVL (SV, Specman e) with UVM/OVM/eRM methodology
  • •Expertise in assertions development/closure, constraint randomization, functional and code coverages, and formal verification
  • •Expertise in test-bench development and strong RTL and GLS (with or without SDF) sim debug skills
  • •Proficiency in Perl/Tcl scripting and automation
Experience:12-14 yearsVLSISemiconductor
Education:Master's
Skills:VerilogHVLUVMOVMSpecman eERMAssertionsConstraint randomizationFormal verificationTestbenchRTLGLSSDFPerlTclAutomation
Tech Stack:VerilogHVLSVSpecmanUVMOVMERMAssertionsConstraint randomizationFormal verificationTestbenchRTLGLSSDFPerlTcl

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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