Cadence Design Systems

1 month ago

Design Engineer - Physical Design

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 6 hours agoStatus: Live

Job Summary

Join Cadence as a Design Engineer focusing on high-speed digital DDR PHY IP physical implementation. You’ll develop scripts to enhance the PD design flow, work on multiple product projects, resolve design issues, and drive PPA optimization by analyzing results and applying optimal design parameters across advanced node processes (TSMC 2nm/3nm/5nm/7nm/12nm, Samsung 2nm/4nm/5nm/7nm/8nm/10nm).

Location: Shanghai

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Focus on high-speed digital DDR PHY IP physical implementation
•Develop necessary scripts or tools to enhance current PD design flow
•Work in product projects, including completing project tasks and solving design issues; provide flow to check and avoid similar issues
•Analyze and summarize PPA optimization methodologies and results; implement optimal design parameters and flows for different projects
•Collaborate with cross-functional teams to ensure timing, power, and area goals are met

Key Requirements

•BS with minimum 4 years of experience; MS with minimum 2 years of experience
•Good physical design experience in the digital implementation domain including Floorplan, CTS, STA, Physical verification, Power analysis
•Solid background in circuits, electronics, physics; willing to learn new technology for cutting-edge process nodes and advanced design methodology
•Skilled in scripting languages such as Perl, C shell, TCL, Makefile, Python
•Familiar with EDA tools like Innovus, ICC, Calibre, Tempus, PrimeTime

Experience:4+ yearsSemiconductorsEDADDRPDIPDigital design

Education:Bachelor's

Skills:PerlC shellTCLMakefilePythonInnovusICCCalibreTempusPrimeTime

Tech Stack:PerlC shellTCLMakefilePythonInnovusICCCalibreTempusPrimeTimeDDR PHYPDEDA

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

1 month ago

Design Engineer - Physical Design

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 6 hours agoStatus: Live

Job Summary

Location: Shanghai

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Focus on high-speed digital DDR PHY IP physical implementation
•Develop necessary scripts or tools to enhance current PD design flow
•Work in product projects, including completing project tasks and solving design issues; provide flow to check and avoid similar issues
•Analyze and summarize PPA optimization methodologies and results; implement optimal design parameters and flows for different projects
•Collaborate with cross-functional teams to ensure timing, power, and area goals are met

Key Requirements

•BS with minimum 4 years of experience; MS with minimum 2 years of experience
•Good physical design experience in the digital implementation domain including Floorplan, CTS, STA, Physical verification, Power analysis
•Solid background in circuits, electronics, physics; willing to learn new technology for cutting-edge process nodes and advanced design methodology
•Skilled in scripting languages such as Perl, C shell, TCL, Makefile, Python
•Familiar with EDA tools like Innovus, ICC, Calibre, Tempus, PrimeTime

Experience:4+ yearsSemiconductorsEDADDRPDIPDigital design

Education:Bachelor's

Skills:PerlC shellTCLMakefilePythonInnovusICCCalibreTempusPrimeTime

Tech Stack:PerlC shellTCLMakefilePythonInnovusICCCalibreTempusPrimeTimeDDR PHYPDEDA

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor