Intern: Application Engineering - Formal Verification

Cadence Design Systems
Belo Horizonte
Workplace: OnsitePart timeFunction: Healthcare (Clinical, Medical, Wellness)Education: bachelorsSkills: ["Communication","Problem-solving","Interpersonal communication","Tcl","Python","Verilog","Vhdl","Rtl verification"]

Intern in Formal Verification within Cadence’s Belo Horizonte team, trained to become an expert in RTL verification using the Jasper platform and Cadence tools (Xcelium, Palladium, Protium). You’ll provide technical support, perform root-cause analysis, run test cases, and collaborate with R&D, while learning scripting (TCL) and verification methodologies on real customer scenarios.

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Cadence Design Systems
Cadence Design Systems
2 months ago

Intern: Application Engineering - Formal Verification

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Last checked: 7 hours agoStatus: Live

Job Summary

Intern in Formal Verification within Cadence’s Belo Horizonte team, trained to become an expert in RTL verification using the Jasper platform and Cadence tools (Xcelium, Palladium, Protium). You’ll provide technical support, perform root-cause analysis, run test cases, and collaborate with R&D, while learning scripting (TCL) and verification methodologies on real customer scenarios.
Location: Belo Horizonte
Workplace: Onsite
Employment Type: Part time
Job Function: Healthcare (Clinical, Medical, Wellness)
Seniority: Entry level

Key Responsibilities

  • •Activities focused on the Formal Verification field, mentored by experienced colleagues, and reporting to higher management.
  • •Provide technical support to customers and field personnel in RTL verification solutions focused on the Jasper tool.
  • •Conduct root cause analysis and provide resolutions to customer technical issues.
  • •Run customer test cases to verify problems, create workarounds when possible, test and deliver R&D fixes.
  • •Close collaboration with R&D using established protocols; author application notes and provide feedback on documentation; use scripting languages like TCL for flow development, automation and enhancing design methodologies.

Key Requirements

  • •Ongoing Bachelor's in Electrical Engineering, Control and Automation Engineering, Systems Engineering, Electronics Engineering, Computer Science, Information Systems, Computational Mathematics, or related areas, graduating mid-2027.
  • •Excellent verbal and written communications skills in Portuguese and English.
  • •Good problem-solving skills and strong interpersonal communication.
  • •A strong interest in learning the technical topics mentioned.
  • •Nice to have: experience with TCL or Python scripting and exposure to RTL (Verilog/VHDL).
Experience:SemiconductorElectronicsVerificationRTLEDA
Education:Bachelor's
Skills:CommunicationProblem-solvingInterpersonal communicationTclPythonVerilogVhdlRtl verification
Languages:PortugueseEnglish
Tech Stack:XceliumPalladiumProtiumJasperVIPsTCLVerilogVHDLPython

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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