Senior Mixed Signal DV Engineer

Texas Instruments
Bengaluru
Workplace: OnsiteFull timeFunction: Solutions Engineering & Sales EngineeringExperience: 12+ yearsEducation: bachelorsSkills: ["Technical leadership","Interpersonal communication","Problem-solving","Analytical thinking","Collaboration"]

Own verification for analog and mixed-signal IC and integrated circuitry designs, confirming adherence to design rules before mask generation. Lead verification strategy with detailed test plans, coverage metrics, and UVM-based environments, using mixed-signal testbenches and analog behavioral modeling. Execute RTL and gate-level simulations, manage regressions, debug complex issues, and support post-silicon pattern generation and characterization for tape-out success.

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Texas Instruments
Texas Instruments
1 day ago

Senior Mixed Signal DV Engineer

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Last checked: 6 hours agoStatus: Live

Job Summary

Own verification for analog and mixed-signal IC and integrated circuitry designs, confirming adherence to design rules before mask generation. Lead verification strategy with detailed test plans, coverage metrics, and UVM-based environments, using mixed-signal testbenches and analog behavioral modeling. Execute RTL and gate-level simulations, manage regressions, debug complex issues, and support post-silicon pattern generation and characterization for tape-out success.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Solutions Engineering & Sales Engineering
Seniority: Mid level

Key Responsibilities

  • •Confirm accuracy of analog and mixed-signal designs before pattern generation/mask development by ensuring adherence to design rules and best practices.
  • •Drive mixed-signal verification strategy by creating test plans, defining test cases/checkers, and establishing coverage metrics with cross-functional partners.
  • •Lead ground-up development of UVM-based verification environments (agents, drivers, monitors, and scoreboards) and build/enhance mixed-signal testbenches using schematics and behavioral models.
  • •Execute RTL and gate-level simulations, manage regressions, and track functional/code coverage to achieve sign-off closure through tape-out.
  • •Debug verification and testbench issues, and support post-silicon ATE functional pattern generation and silicon characterization.

Key Requirements

  • •BS or equivalent experience in electrical engineering and at least 12 years of experience.
  • •Strong expertise in SystemVerilog (SV) and UVM methodologies.
  • •Proficiency in mixed-signal verification flows using schematics, behavioral models, and RTL.
  • •Experience with analog behavioral modeling using Verilog-AMS, Verilog-A, or Wreal (RNM).
  • •Hands-on verification skills with Formal Property Verification (FPV), including connectivity checks and Unreachability analysis.
Experience:12+ years
Education:Bachelor's in electrical engineering
Skills:Technical leadershipInterpersonal communicationProblem-solvingAnalytical thinkingCollaboration
Tech Stack:SystemVerilogUVMVerilog-AVerilog-AMSWreal (RNM)EENetCadence XceliumCadence vManagerJasperGoldCadence VirtuosoAMS DesignerUPFFormal Property Verification (FPV)CDCRDCRTLGate-Level Simulations (GLS)PythonPerlShell scripting

Company Brief

Texas Instruments
Designs and manufactures semiconductors and analog chips used in industrial, automotive, personal electronics, communications, and enterprise systems. It is one of the world’s largest semiconductor companies, with a broad portfolio of embedded processing and power products.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Dallas, United States
Founded: 1930
WebsiteLinkedIn