ASIC DFT Engineering Technical Leader | ATPG, SCAN, MBIST, JTAG | 12+ years, Bangalore

Cisco
Bengaluru, Hyderabad
Workplace: HybridFull timeFunction: Hardware, Embedded & Systems EngineeringExperience: 12+ yearsEducation: mastersSkills: ["Collaboration","Technical leadership"]

Lead ASIC implementation in Cisco’s Silicon One organization with a focus on design-for-test. Partner with RTL and back-end physical design teams to define DFT requirements early, drive DFT and quality processes across implementation and post-silicon validation, and support signoff activities. Own DFT/verification strategy, reusable infrastructure, electrical interface planning, and verification/validation activities using ATPG, JTAG/SCAN/MBIST, and industry EDA and simulation tools.

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FursaFursa
Cisco
Cisco
1 day ago

ASIC DFT Engineering Technical Leader | ATPG, SCAN, MBIST, JTAG | 12+ years, Bangalore

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Job Summary

Lead ASIC implementation in Cisco’s Silicon One organization with a focus on design-for-test. Partner with RTL and back-end physical design teams to define DFT requirements early, drive DFT and quality processes across implementation and post-silicon validation, and support signoff activities. Own DFT/verification strategy, reusable infrastructure, electrical interface planning, and verification/validation activities using ATPG, JTAG/SCAN/MBIST, and industry EDA and simulation tools.
Location: Bengaluru, Hyderabad
Workplace: Hybrid
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Sr. Manager level

Key Responsibilities

  • •Lead the definition, architecture, and design of high-performance ASICs with a primary focus on design-for-test.
  • •Drive DFT and quality processes across the ASIC implementation flow and post-silicon validation phases, including exposure to physical design signoff activities.
  • •Coordinate with front-end RTL and backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle.
  • •Own reusable code/infrastructure for verification and testing, and oversee verification strategies and integration into PD and DV flows.
  • •Develop test solutions, build first test vehicles, and perform verification/validation while interfacing with vendors and design leads for timing closure and electrical interface planning.

Key Requirements

  • •Bachelor’s or Master’s degree in Electrical or Computer Engineering with at least 12+ years of experience.
  • •Experience with JTAG protocols (p1500, p1687), scan insertion, and BIST architectures including memory BIST and boundary scan.
  • •Experience with ATPG and EDA tools such as TestMax, Tetramax, and Tessent, including test static timing analysis constraints and timing closure.
  • •Experience with gate-level simulation and timing-based simulations using SDF, with debugging using VCS and other simulators.
  • •Post-silicon validation and debug experience; ability to work with ATE engineers on pattern translation and validation.
Experience:12+ yearsASICSemiconductorsDesign-for-test (DFT)Networking hardware
Education:Master's in Electrical or Computer Engineering
Skills:CollaborationTechnical leadership
Tech Stack:JTAGP1500P1687Scan insertionMBISTBoundary scanATPGTestMaxTetramaxTessentStatic timing analysisGate-level simulationSDFVCSTclPythonPerlVerilogATEPattern translation

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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