Sr. Principal Software Engineer
Cadence Design Systems
Austin
Workplace: OnsiteFull timeUSD 196,000 - 364,000 annuallyFunction: Software EngineeringEducation: mastersSkills: ["C","C++","Unix","Linux","Verilog","VHDL","Design-for-Test","VLSI","Algorithms","Data structures"]Design and develop Design-for-Test software within the Modus R&D Front-End Design team for VLSI Design Automation. Focus on DFT logic insertion and verification, leveraging C/C++ on UNIX/Linux, with Verilog/VHDL familiarity. Join a distributed, high-impact group delivering large-scale software projects and solutions for testability in advanced silicon.
