DFT Architect

AMD
San Jose
Workplace: OnsiteFull timeFunction: Hardware, Embedded & Systems EngineeringEducation: phdSkills: ["Leadership","Cross-functional communication","Collaboration","Group work","Communication"]

Drive DFT architecture definitions for Scan, MBIST, PHY, high-speed/high-density I/Os, communication controllers, and FPGA logic for future AMD products. Partner with design architects, DFT/DFX and block owners, and physical design teams across ATE manufacturing, silicon debug, and quality/test cost perspectives. Oversee early architecture design definition through DFT implementation completion and successful high-volume silicon production.

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FursaFursa
AMD
AMD
1 week ago

DFT Architect

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Last checked: 5 hours agoStatus: Live
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Job Summary

Drive DFT architecture definitions for Scan, MBIST, PHY, high-speed/high-density I/Os, communication controllers, and FPGA logic for future AMD products. Partner with design architects, DFT/DFX and block owners, and physical design teams across ATE manufacturing, silicon debug, and quality/test cost perspectives. Oversee early architecture design definition through DFT implementation completion and successful high-volume silicon production.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering

Key Responsibilities

  • •Promote ATE/production test environment improvements, including test cost and test quality, through DFT architecture definitions and specifications.
  • •Manage DFT activities across architecture, design implementation, verification, and test implementation for new products.
  • •Drive global quality/manufacturing best-test solutions through early product definition and pre-/post-silicon activities.
  • •Ensure DFT structures are correctly implemented with design teams.
  • •Plan for diagnosability and yield improvement; drive firmware-driven test solutions.

Key Requirements

  • •Significant DFT engineering experience across pre- and post-silicon cycles.
  • •Experience creating and implementing complex chip-level DFT architecture.
  • •DFT implementation experience including Scan and Scan Compression at IP and SoC level.
  • •Hands-on knowledge of DFT tools and ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression.
  • •Strong MBIST knowledge and understanding of verification methodology.
Education:PhD / Doctorate in Electrical/Electronic/Computer Engineering
Skills:LeadershipCross-functional communicationCollaborationGroup workCommunication
Languages:English
Tech Stack:DFTDFXScanMBISTPHYHigh-speed IODigital communicationFunctional test developmentTessent Streaming Scan Network (SSN)VerilogSynthesisPhysical implementationSTAATPGStuck-AtAt-SpeedPath-DelayScan compressionFPGAFirmware

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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