Senior ASIC Physical Design Engineering Technical Lead

Lead full-chip physical design for ASICs, driving floorplanning, clocking, power integrity, and sign-off workflows from RTL to GDSII. Collaborate with RTL/DFT, EDA vendors, and foundry teams to optimize performance, power, and die size, leveraging UPF-based low-power methods and AI-assisted productivity improvements within Cisco’s CHG hardware team.