Memory Layout Design Engineer

Cisco
Yerevan
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Experience: 4+ yearsEducation: high_schoolSkills: ["Clear communication","Collaboration","Independent work","Cross-functional teamwork","English communication"]

Implement high-quality SRAM memory layout for the Cisco Silicon One platform, translating schematics into robust physical designs for core networking products. Perform post-layout simulations, fix issues to maintain clean DRC, and optimize layouts for quality, visibility, and delivery velocity. Work closely with international circuit design teams to ensure reliable integration across neighboring modules using industry-standard EDA workflows.

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FursaFursa
Cisco
Cisco
2 days ago

Memory Layout Design Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 10 hours agoStatus: Live
Reposted: similar role first listed 3 weeks ago

Job Summary

Implement high-quality SRAM memory layout for the Cisco Silicon One platform, translating schematics into robust physical designs for core networking products. Perform post-layout simulations, fix issues to maintain clean DRC, and optimize layouts for quality, visibility, and delivery velocity. Work closely with international circuit design teams to ensure reliable integration across neighboring modules using industry-standard EDA workflows.
Location: Yerevan
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Implement high-quality memory layout, focusing on SRAM blocks to meet performance and reliability standards.
  • •Collaborate with international circuit design teams to translate schematics into robust physical designs.
  • •Run post-layout simulations and apply corrections to ensure DRC cleanliness and optimal integration with neighboring modules.
  • •Optimize layout designs for quality, visibility, and delivery velocity for critical silicon components.
  • •Support tapeouts by contributing to technical closure activities as needed.

Key Requirements

  • •Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • •4+ years of professional experience in physical design or layout.
  • •Experience with industry-standard EDA tools such as Cadence or Synopsys.
  • •Experience with advanced node technologies such as TSMC 22nm, 12nm, 7nm, 5nm, or 2nm.
  • •Knowledge of scripting languages (Tcl, Python, or Perl) for design automation.
Experience:4+ yearsPhysical designMemory layoutMixed-signalCustom design
Education:High School in Electrical Engineering, Computer Engineering, or a related field
Skills:Clear communicationCollaborationIndependent workCross-functional teamworkEnglish communication
Languages:English
Tech Stack:CadenceSynopsysTSMC 22nmTSMC 12nmTSMC 7nmTSMC 5nmTSMC 2nmSRAMDRCEMIR/ERC closureTclPythonPerl

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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