Sr. RFIC Layout Designer (RFIC Engineering)

Lead RFIC and analog IC layout for multiple silicon projects, partnering with circuit designers, chip leads, and packaging engineers to define chip floorplans and pad locations. Execute custom layout with strong attention to matching and minimizing parasitics, perform DRC/ERC and layout-versus-schematic checks, and integrate top-level layouts including ESD structures and tape-out deliverables. Evaluate new EDA tools, and create guides and demos to improve layout techniques.