Sr. RFIC Layout Designer (RFIC Engineering)

SpaceX
Irvine, Palo Alto, Redmond
Workplace: OnsiteFull timeFunction: Hardware, Embedded & Systems EngineeringEducation: bachelorsSkills: ["Communication","Independent work"]

Lead RFIC and analog IC layout for multiple silicon projects, partnering with circuit designers, chip leads, and packaging engineers to define chip floorplans and pad locations. Execute custom layout with strong attention to matching and minimizing parasitics, perform DRC/ERC and layout-versus-schematic checks, and integrate top-level layouts including ESD structures and tape-out deliverables. Evaluate new EDA tools, and create guides and demos to improve layout techniques.

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FursaFursa
SpaceX
SpaceX
1 month ago

Sr. RFIC Layout Designer (RFIC Engineering)

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Last checked: 15 hours agoStatus: Live

Job Summary

Lead RFIC and analog IC layout for multiple silicon projects, partnering with circuit designers, chip leads, and packaging engineers to define chip floorplans and pad locations. Execute custom layout with strong attention to matching and minimizing parasitics, perform DRC/ERC and layout-versus-schematic checks, and integrate top-level layouts including ESD structures and tape-out deliverables. Evaluate new EDA tools, and create guides and demos to improve layout techniques.
Location: Irvine, Palo Alto, Redmond
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Collaborate with IC designers and chip leads to determine chip floorplans, including power/ground distribution strategies and pad locations with the packaging engineer.
  • •Estimate layout schedules and identify complexity areas early for investigation.
  • •Perform layout of custom RF and analog circuit blocks, emphasizing matching and minimizing parasitic capacitance.
  • •Run design rule checking (DRC), electrical rule checking (ERC), and layout-versus-schematic checks; resolve errors.
  • •Integrate top-level layouts with ESD structures and pad assembly, perform tape-out deliverables (including density fill and DFM checks), and share GDS with the foundry.

Key Requirements

  • •Bachelor’s degree in electrical or computer engineering with 5+ years as an IC layout designer, or 8+ years of IC layout experience in lieu of a degree.
  • •Strong analog layout skills with experience in advanced node IC layouts (22nm, 16nm, 7nm, 5nm or below).
  • •Experience laying out RF circuits up to 50GHz and sensitive RF blocks such as LNAs, VCOs, and mixers.
  • •Experience performing DRC/ERC and layout versus schematic checks, and resolving layout errors.
  • •Working knowledge of Linux plus strong communication skills.
Education:Bachelor's in electrical or computer engineering
Skills:CommunicationIndependent work
Tech Stack:LinuxPerlPythonShell scriptingEDAGDS

Eligibility

Nationality:US National

Company Brief

SpaceX
Designs, manufactures, and launches advanced rockets and spacecraft for commercial and government customers, aiming to reduce space transportation costs and enable human life on Mars through reusable launch vehicles and integrated space systems.
Industry: Aerospace Manufacturing
Company Size: Enterprise (1,001+ employees)
Growth: Established Company
Valuation: Hectocorn (USD 100B+)
Funding: Series E+
Headquarters: Hawthorne, United States
Founded: 2002
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