Intel

1 month ago

Senior Analog Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Senior Analog Design Engineer needed to design, develop, and optimize analog and mixed-signal ICs for Intel’s High-Speed IO and die-to-die interfaces. Lead projects from concept to production, mentor juniors, collaborate cross-functionally across global teams, and drive silicon validation and performance optimization in a hybrid on-site role with multiple US locations.

Location: Phoenix

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Design and simulate analog and mixed-signal circuits including amplifiers, data converters, voltage regulators, PLLs, and other analog building blocks; create and optimize layouts with layout engineers
•Lead analog design projects from specification to silicon validation; mentor junior engineers and collaborate with cross-functional teams
•Develop test plans and oversee silicon characterization; debug design issues during pre- and post-silicon phases; optimize for performance, power, and area
•Drive design reviews, ensure adherence to methodologies, and coordinate with teams across US and India for design interoperability
•Work in a hybrid model, collaborating with system architects, logic, verification, physical design, and SOC partners to deliver high-quality interconnect designs

Pay and Benefits

Salary: USD 190,610 - 269,100 annually

Perks:Health InsurancePensionEquityRelocation401kPaid LeaveHybrid Work

Key Requirements

•Bachelor's degree in Electrical Engineering, Electronics Engineering, or related field; 6+ years in analog/mixed-signal circuit design for high-speed SerDes or similar applications
•Proven experience in PLL, CDR, CTLE, DFE, ADC, RX AFE, Transmitter, Power Delivery design, IP floor planning, top-level performance simulation, and signal integrity analysis
•High-speed IO calibration and training algorithms; knowledge of PCIe Gen5/Gen6/Gen7; UCIE standards
•Hands-on experience with FinFET CMOS process technologies; Cadence Virtuoso/ADE, HSPICE or equivalent for design and simulation
•Post-silicon validation, lab measurements, and debugging of analog circuits; strong communication, documentation, and cross-functional collaboration

Experience:6+ yearsSemiconductorsAnalog designHigh-speed IOPCIeSerDesMixed-signal

Education:Bachelor's

Skills:CommunicationTeamworkMentoringDocumentationProblem-solving

Tech Stack:CadenceSynopsysCadence VirtuosoADEHSPICEVerilog-AMATLABPython

Company Brief

Intel

Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1968

Glassdoor: 3.8

Website LinkedIn Glassdoor

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Intel

1 month ago

Senior Analog Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Location: Phoenix

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Design and simulate analog and mixed-signal circuits including amplifiers, data converters, voltage regulators, PLLs, and other analog building blocks; create and optimize layouts with layout engineers
•Lead analog design projects from specification to silicon validation; mentor junior engineers and collaborate with cross-functional teams
•Develop test plans and oversee silicon characterization; debug design issues during pre- and post-silicon phases; optimize for performance, power, and area
•Drive design reviews, ensure adherence to methodologies, and coordinate with teams across US and India for design interoperability
•Work in a hybrid model, collaborating with system architects, logic, verification, physical design, and SOC partners to deliver high-quality interconnect designs

Pay and Benefits

Salary: USD 190,610 - 269,100 annually

Perks:Health InsurancePensionEquityRelocation401kPaid LeaveHybrid Work

Key Requirements

•Bachelor's degree in Electrical Engineering, Electronics Engineering, or related field; 6+ years in analog/mixed-signal circuit design for high-speed SerDes or similar applications
•Proven experience in PLL, CDR, CTLE, DFE, ADC, RX AFE, Transmitter, Power Delivery design, IP floor planning, top-level performance simulation, and signal integrity analysis
•High-speed IO calibration and training algorithms; knowledge of PCIe Gen5/Gen6/Gen7; UCIE standards
•Hands-on experience with FinFET CMOS process technologies; Cadence Virtuoso/ADE, HSPICE or equivalent for design and simulation
•Post-silicon validation, lab measurements, and debugging of analog circuits; strong communication, documentation, and cross-functional collaboration

Experience:6+ yearsSemiconductorsAnalog designHigh-speed IOPCIeSerDesMixed-signal

Education:Bachelor's

Skills:CommunicationTeamworkMentoringDocumentationProblem-solving

Tech Stack:CadenceSynopsysCadence VirtuosoADEHSPICEVerilog-AMATLABPython

Company Brief

Intel

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1968

Glassdoor: 3.8

Website LinkedIn Glassdoor