Senior Hardware Design Engineer

Arago
Paris, Tel Aviv
Workplace: OnsiteFull timeFunction: Hardware, Embedded & Systems EngineeringSkills: ["Debugging","Collaboration"]

Design and verify custom digital hardware components and architectures for high-performance, tightly integrated computation workloads. You’ll develop RTL blocks (memory, control, compute), define block-level specifications with system software and architecture teams, and build functional verification infrastructure across simulation and hardware testbenches. Support synthesis, timing analysis, and backend integration, and contribute to architectural exploration and hardware-software co-design for future iterations of the compute platform.

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FursaFursa
Arago
Arago
3 days ago

Senior Hardware Design Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 4 hours agoStatus: Live
Reposted: similar role first listed 7 months ago

Job Summary

Design and verify custom digital hardware components and architectures for high-performance, tightly integrated computation workloads. You’ll develop RTL blocks (memory, control, compute), define block-level specifications with system software and architecture teams, and build functional verification infrastructure across simulation and hardware testbenches. Support synthesis, timing analysis, and backend integration, and contribute to architectural exploration and hardware-software co-design for future iterations of the compute platform.
Location: Paris, Tel Aviv
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Design, implement, and verify RTL blocks for memory, control, and compute subsystems in Arago’s custom multiphysics computation unit.
  • •Collaborate with system software and architecture teams to define block-level specifications and align with performance and integration goals.
  • •Develop and maintain functional verification infrastructure to validate correctness across simulation and hardware testbenches.
  • •Support synthesis, timing analysis, and backend integration with physical design and CAD engineers.
  • •Contribute to architectural exploration and hardware-software co-design efforts for future compute platform iterations.

Pay and Benefits

Perks:EquityAnnual BonusHealth InsurancePensionPaid LeaveCommuter Benefits

Key Requirements

  • •Extensive RTL design experience in Verilog/SystemVerilog for control logic, datapaths, memory subsystems, and specialized processing units.
  • •Strong understanding of digital architecture, including pipelining, arbitration, memory hierarchy, and system-level integration.
  • •Proficiency in functional verification, including testbench development, assertions, coverage metrics, and debugging (UVM experience is a plus).
  • •Familiarity with ASIC and FPGA design flows, including synthesis, timing closure, and DFT.
  • •Comfort working across the hardware stack, from architectural specification and microarchitecture to physical implementation support.
Experience:AISemiconductorsASICFPGA
Skills:DebuggingCollaboration
Languages:EnglishFrench
Tech Stack:RTLVerilogSystemVerilogUVMASICFPGASynthesisTiming analysisDFTTestbenches

Company Brief

Arago
Develops energy-efficient photonic AI processors (codenamed “JEF”) that use light-based computation to drastically reduce energy consumption for AI workloads, targeting data centers and large-scale inference deployments.
Industry: Deep Tech
Company Size: Small (11 to 50 employees)
Growth: Early Stage Startup
Funding: Seed
Headquarters: Paris, France
Founded: 2024
Glassdoor
Glassdoor: 3.9
WebsiteGlassdoor