Sr Engineer, Advanced Packaging Design Enablement Engineering (APDEE)

Micron Technology
Hyderabad
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsSkills: []

Drive advanced packaging build enablement for High Bandwidth Memory (HBM) programs, partnering across silicon design and packaging teams to deliver optimized cost, quality, reliability, and time-to-market. Execute packaging-related design strategy including PWF reticle design, DFT development for packaging fail modes, test structure enablement, and DFMEA maintenance. Lead BEOL engagement, TSV design collaboration, and electrical simulations to understand fail modes and improve 3D integration performance.

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FursaFursa
Micron Technology
Micron Technology
3 months ago

Sr Engineer, Advanced Packaging Design Enablement Engineering (APDEE)

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Source: Company careers pageValidated by: Fursa AI
Last checked: 15 hours agoStatus: Live

Job Summary

Drive advanced packaging build enablement for High Bandwidth Memory (HBM) programs, partnering across silicon design and packaging teams to deliver optimized cost, quality, reliability, and time-to-market. Execute packaging-related design strategy including PWF reticle design, DFT development for packaging fail modes, test structure enablement, and DFMEA maintenance. Lead BEOL engagement, TSV design collaboration, and electrical simulations to understand fail modes and improve 3D integration performance.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Build and tapeout PWF reticles design for packaging programs.
  • •Develop DFTs in test vehicles for packaging-related fail modes.
  • •Coordinate with HIG-HBM teams to build test structures for live die and support packaging design enablement.
  • •Manage design rules for PWF, wafer thinning and dicing, and die stacking; engage with BEOL and scribe design teams.
  • •Create and maintain DFMEA for advanced packaging process steps and perform electrical simulations to understand fail mode mechanisms.

Key Requirements

  • •5+ years of experience in die design and physical layout engineering.
  • •Hands-on experience with HBM, 3D-IC, or advanced packaging programs (CoWoS, SoIC, FOVEROS, or equivalent).
  • •Proven TSV-based die design experience including KOZ management, micro-bump layout, and backside RDL.
  • •Deep expertise in physical design and layout using EDA tools such as Cadence Virtuoso, Innovus, Mentor Calibre, and Synopsys IC Compiler.
  • •Masters or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
Experience:5+ yearsSemiconductorsHBM3D-ICAdvanced packagingTSV3D integration
Education:
Tech Stack:Cadence VirtuosoInnovusMentor CalibreSynopsys IC CompilerSkillPythonTclIEEE P1838HBM2EHBM3HBM3EJEDECDRCLVSERCDFMEA

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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