DFT Verification Engineer

NVIDIA
Bengaluru
Workplace: HybridFull timeFunction: QA, Test & Release EngineeringExperience: 2+ yearsEducation: bachelorsSkills: ["Analytical thinking","Problem-solving","Collaboration"]

Own end-to-end DFX verification, pattern development, and silicon bring-up for test features including JTAG, boundary scan, security mechanisms, and reliability tests (HTOL/IDDQ) across multiple ATPG configurations in multi-die environments. Partner with DFX, CAD, and methodology teams to improve verification flows and processes, develop and deploy DFT methodologies for next-generation products, and integrate DFT features into chips while driving quality improvements in test methods and AI deployment.

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FursaFursa
NVIDIA
NVIDIA
4 days ago

DFT Verification Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 21 hours agoStatus: Live

Job Summary

Own end-to-end DFX verification, pattern development, and silicon bring-up for test features including JTAG, boundary scan, security mechanisms, and reliability tests (HTOL/IDDQ) across multiple ATPG configurations in multi-die environments. Partner with DFX, CAD, and methodology teams to improve verification flows and processes, develop and deploy DFT methodologies for next-generation products, and integrate DFT features into chips while driving quality improvements in test methods and AI deployment.
Location: Bengaluru
Workplace: Hybrid
Employment Type: Full time
Job Function: QA, Test & Release Engineering
Seniority: Mid level

Key Responsibilities

  • •Take end-to-end ownership of DFX verification, pattern development, and silicon bring-up for multiple test features across test modes and ATPG configurations.
  • •Collaborate with DFX teams, CAD, and methodology teams to improve verification flows and processes.
  • •Develop and deploy DFT methodologies for next-generation products.
  • •Drive continuous improvement in the quality of DFT methods and AI deployment in the processes.
  • •Work with multi-functional teams to incorporate DFT features into the chip.

Key Requirements

  • •BSEE or MSEE (or equivalent experience) with 2+ years of experience.
  • •Proficiency in static timing analysis, ECO, ASIC/logic design flow, HDL, and digital logic design.
  • •Experience in RTL and gates verification, simulation, and silicon bring-up.
  • •Familiarity with BIST architecture and JTAG/IEEE1149.1/1500/1687/1838.
  • •Strong DFT knowledge in scan ATPG, compression techniques, and memory test, plus analytical problem-solving and scripting (Perl/Python).
Experience:2+ years
Education:Bachelor's
Skills:Analytical thinkingProblem-solvingCollaboration
Tech Stack:DFX verificationPattern developmentSilicon bring-upJTAGBoundary scanSecurity mechanismsHTOLIDDQTest clockingATPGMulti-dieDFT methodologiesCADStatic timing analysisECOASIC/Logic Design FlowHDLDigital logic designRTLGates verification

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
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Glassdoor: 4.3
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