Design Verification Engineer (Silicon Engineering)

Develop and execute digital ASIC verification across block and system levels for next-generation chips used in space and ground infrastructure. Create and review test plans, build SystemVerilog testbench infrastructure (UVM and non-UVM), run regressions, and drive code and functional coverage closure. Automate test case generation using Python and MATLAB, and contribute to pre-silicon verification, chip bring-up, and post-silicon validation within cross-disciplinary teams.