SoC Physical Design Lead

AMD
Hyderabad
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Education: mastersSkills: ["Communication","Presentation","Collaboration","Mentoring","Risk mitigation"]

Own end-to-end physical design for high-performance, low-power SoCs, including floorplanning, placement, clock tree synthesis, routing, and timing closure. Define and optimize PnR strategies for advanced nodes (5nm/3nm/2nm) while balancing PPA targets. Drive sign-off criteria and waiver processes, introduce innovations for congestion, timing, and power integrity, and partner across RTL, architecture, CAD, and verification to resolve design challenges, manage ECO readiness, and support tapeout-critical risk mitigation.

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FursaFursa
AMD
AMD
1 month ago

SoC Physical Design Lead

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Source: Company careers pageValidated by: Fursa AI
Last checked: 6 hours agoStatus: Live
Reposted: similar role first listed 8 months ago

Job Summary

Own end-to-end physical design for high-performance, low-power SoCs, including floorplanning, placement, clock tree synthesis, routing, and timing closure. Define and optimize PnR strategies for advanced nodes (5nm/3nm/2nm) while balancing PPA targets. Drive sign-off criteria and waiver processes, introduce innovations for congestion, timing, and power integrity, and partner across RTL, architecture, CAD, and verification to resolve design challenges, manage ECO readiness, and support tapeout-critical risk mitigation.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Own end-to-end physical design for high-performance, low-power SoCs (floorplanning, placement, clock tree synthesis, routing, timing closure).
  • •Define and optimize PnR strategies for advanced nodes (e.g., 5nm/3nm/2nm) balancing performance, power, and area (PPA).
  • •Establish and drive sign-off criteria and waiver processes.
  • •Introduce innovative techniques for congestion management, timing optimization, and power integrity.
  • •Partner with RTL, architecture, CAD, and verification teams to resolve design challenges; influence partitioning, interface planning, and hierarchical strategies to meet schedules; manage ECO delivery risks and publish risk burndown/mitigation plans for tapeout-critical paths.

Key Requirements

  • •15+ years of experience in relevant domain.
  • •Proficiency with EDA tools including Innovus, Fusion compiler/ICCompiler2, and Primetime.
  • •Experience owning end-to-end physical design for high-performance, low-power SoCs (floorplanning, placement, clock tree synthesis, routing, timing closure).
  • •Ability to define and optimize PnR strategies for advanced nodes (e.g., 5nm/3nm/2nm) balancing performance, power, and area (PPA).
  • •Bachelors or Masters degree in computer engineering or Electrical Engineering.
Experience:SoCPhysical designEDAHigh-performance computingAICloud
Education:Master's in computer engineering/Electrical Engineering
Skills:CommunicationPresentationCollaborationMentoringRisk mitigation
Languages:En-us
Tech Stack:SoCsPPAPnRFloorplanningPlacementClock tree synthesisRoutingTiming closureInnovusFusion compilerICCompiler2PrimetimeRTLCADVerificationECO

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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