SoC Physical Design Lead

Own end-to-end physical design for high-performance, low-power SoCs, including floorplanning, placement, clock tree synthesis, routing, and timing closure. Define and optimize PnR strategies for advanced nodes (5nm/3nm/2nm) while balancing PPA targets. Drive sign-off criteria and waiver processes, introduce innovations for congestion, timing, and power integrity, and partner across RTL, architecture, CAD, and verification to resolve design challenges, manage ECO readiness, and support tapeout-critical risk mitigation.