Principal Collateral Device Engineer

Intel
United States
Workplace: HybridFull timeUSD 224,970 - 317,600 annuallyFunction: Communications, PR & CommunityExperience: 15+ yearsEducation: mastersSkills: ["Technical problem-solving","Cross-functional collaboration","Data analysis","Leadership","Influence"]

Lead device collateral development for Intel Foundry within MDCE, ensuring world-class process device performance for next-generation device and interconnect technology. Define derivative architectures (design rules, transistors, interconnects), develop scribe-line and process monitoring structures, and manage design rule validation/waivers. Partner across Process Integration, Yield, Device, and Design, using test chip data analysis, DOE, and statistical methods to optimize performance and support high-volume manufacturing.

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FursaFursa
Intel
Intel
2 months ago

Principal Collateral Device Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 6 hours agoStatus: Live
Reposted: similar role first listed 1 month ago

Job Summary

Lead device collateral development for Intel Foundry within MDCE, ensuring world-class process device performance for next-generation device and interconnect technology. Define derivative architectures (design rules, transistors, interconnects), develop scribe-line and process monitoring structures, and manage design rule validation/waivers. Partner across Process Integration, Yield, Device, and Design, using test chip data analysis, DOE, and statistical methods to optimize performance and support high-volume manufacturing.
Location: United States
Workplace: Hybrid
Employment Type: Full time
Job Function: Communications, PR & Community
Seniority: Mid level

Key Responsibilities

  • •Lead cross-functional efforts to define derivative architectures including design rules, transistors, and interconnects.
  • •Develop scribe line layout design and process monitoring structure development.
  • •Create and validate design rules, including waiver management processes.
  • •Serve as the key interface between Process Integration, Yield, Device, and Design, including DTCO understanding.
  • •Analyze test chip data using scripting and statistical techniques and apply DOE principles to optimize device collateral.

Pay and Benefits

Salary: USD 224,970 - 317,600 annually
Perks:Health InsuranceRetirementPaid Leave

Key Requirements

  • •Master’s degree in Electrical Engineering, Physics, or a related field.
  • •15+ years of experience in CMOS device engineering focused on test chip design and device collateral development.
  • •Experience in advanced node test chip design and scribe line optimization for 3nm–16nm FinFETs and sub-3nm GAA FETs.
  • •Experience with design rule checker (DRC) development and physical verification flows.
  • •Knowledge of statistical process control (SPC) and advanced data analytics for device collateral optimization.
Experience:15+ yearsSemiconductor manufacturingCMOS device engineeringTest chip designFinFETGAA FETHigh-volume manufacturing
Education:Master's in Electrical Engineering, Physics, or related field
Skills:Technical problem-solvingCross-functional collaborationData analysisLeadershipInfluence
Tech Stack:CMOSFinFETGAA FETSRAMStandard cellsDesign rulesDRCDOESPCOPCMask generationDTCOScribe lineTest chip designProcess monitoring structuresWaiver management

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
Glassdoor
Glassdoor: 3.8
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