Physical Design Engineer - Block Level, Subsystem Implementation

Etched
Austin, San Jose
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 5-10 yearsSkills: ["Creativity","First-principles thinking","Collaboration","Debugging","Continuous improvement"]

Own block-level physical design end to end for frontier inference clusters, from floorplanning and synthesis through routing and GDSII sign-off. Drive timing closure across corners and modes, handle sign-off quality (EM/IR drop, RC extraction/correlation, DRC/LVS/antenna), and produce abstracts/views/timing budgets for hierarchical integration. Partner with RTL designers to improve PPA and continuously advance the shared RTL-to-GDSII flow, including supervising outsourced PD work.

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FursaFursa
Etched
Etched
1 month ago

Physical Design Engineer - Block Level, Subsystem Implementation

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Last checked: 15 hours agoStatus: Live

Job Summary

Own block-level physical design end to end for frontier inference clusters, from floorplanning and synthesis through routing and GDSII sign-off. Drive timing closure across corners and modes, handle sign-off quality (EM/IR drop, RC extraction/correlation, DRC/LVS/antenna), and produce abstracts/views/timing budgets for hierarchical integration. Partner with RTL designers to improve PPA and continuously advance the shared RTL-to-GDSII flow, including supervising outsourced PD work.
Location: Austin, San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Own block-level and/or subsystem physical design end to end, including floorplanning, synthesis, placement, clock tree synthesis, and routing through GDSII.
  • •Drive block-level timing closure across corners and modes, including constraint development, STA debug, and functional/timing ECO implementation.
  • •Complete block-level signoff across EM, IR drop, RC extraction/correlation, and physical verification (DRC, LVS, antenna).
  • •Generate abstracts, views, and timing budgets for hierarchical integration of blocks into the top level.
  • •Collaborate with RTL designers and provide physical design feedback to improve PPA; supervise outsourced physical design work for quality and closure.

Pay and Benefits

Perks:Health InsuranceDentalVisionHousing SubsidyRelocation SupportMeal AllowanceWellness Stipend

Key Requirements

  • •5-10+ years of previous experience with physical design (PD).
  • •Experience with tools, flows, and methodology from RTL synthesis through GDSII sign-off.
  • •Back-end design and timing closure experience on advanced process nodes (5nm and below).
  • •Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows.
  • •Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.) and UPF-based low power design methodology, including verification and EM/antenna analysis.
Experience:5-10 yearsAI hardwareInferenceMLLLMFrontier AI
Skills:CreativityFirst-principles thinkingCollaborationDebuggingContinuous improvement
Tech Stack:GDSIICadence InnovusCadence GenusSynopsys Fusion CompilerPrimeTimeTempusVoltusUPFTclPythonPerlTSTASTAECODRCLVSAntenna analysisEM/IR dropRC extractionATPG

Company Brief

Etched
Designs transformer‑specialized AI inference ASICs (product: Sohu) to accelerate large‑language‑model workloads, working with TSMC for fabrication and targeting energy‑efficient inference performance.
Industry: Hardware Devices
Company Size: Medium (51 to 250 employees)
Growth: Early Stage Startup
Valuation: Unicorn (USD 1B+)
Funding: Series A
Headquarters: San Jose, United States
Founded: 2022
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