DFx Verification

AMD
Bengaluru
Full timeINR 2,186,520 - 3,123,600 annuallyFunction: Hardware, Embedded & Systems EngineeringSkills: ["Communication","Teamwork","Analytical skills","Problem-solving","Collaboration","Willingness to learn"]

Own DFx verification across block/IP, subsystem, and SoC levels, including scan/ATPG, LBIST/MBIST, JTAG/IEEE 1149.x, boundary scan, and test compression. Build and maintain SystemVerilog/UVM testbenches with stimulus, checkers, coverage, and scoreboards, define verification plans, and close gaps using coverage-driven metrics. Develop BFMs/agents/monitors, run gate-level simulations with SDF, partner with DFT/DFx architects and RTL designers, and support silicon bring-up, debug, and yield improvements. Automate regressions, debugging, and CI dashboards.

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FursaFursa
AMD
AMD
1 day ago

DFx Verification

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Source: Company careers pageValidated by: Fursa AI
Last checked: 20 hours agoStatus: Live

Job Summary

Own DFx verification across block/IP, subsystem, and SoC levels, including scan/ATPG, LBIST/MBIST, JTAG/IEEE 1149.x, boundary scan, and test compression. Build and maintain SystemVerilog/UVM testbenches with stimulus, checkers, coverage, and scoreboards, define verification plans, and close gaps using coverage-driven metrics. Develop BFMs/agents/monitors, run gate-level simulations with SDF, partner with DFT/DFx architects and RTL designers, and support silicon bring-up, debug, and yield improvements. Automate regressions, debugging, and CI dashboards.
Location: Bengaluru
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Own DFx verification at block/IP, subsystem, and SoC levels across scan/ATPG, LBIST/MBIST, JTAG/IEEE 1149.x, boundary scan, test compression, repair, and debug.
  • •Develop and maintain SystemVerilog/UVM testbenches and tests for DFx, including stimulus, checkers, coverage, and scoreboards.
  • •Define and execute DFx verification plans, tracking and closing using coverage-driven metrics.
  • •Build and maintain BFMs, agents, and monitors to verify interactions between DFx logic and key functional blocks (clocks, resets, power, fabric, memories).
  • •Partner with DFT/DFx architects and RTL designers, and support silicon bring-up by correlating pre-silicon results with silicon, enabling pattern debug, and improving yield/quality.

Pay and Benefits

Salary: INR 2,186,520 - 3,123,600 annually

Key Requirements

  • •Strong experience in digital design verification using SystemVerilog and UVM (or similar verification methodologies).
  • •Hands-on experience with DFT/DFx concepts and flows such as Scan, test compression, and ATPG patterns.
  • •Experience with logic BIST (LBIST) and memory BIST (MBIST), including JTAG/IEEE 1149.x and boundary scan/test access mechanisms.
  • •Understanding of complex SoC/CPU/GPU or ASIC design, including clocks, resets, CDC, and power intent (UPF/low-power modes) as related to DFx.
  • •Bachelor’s or Master’s degree in computer engineering or electrical engineering.
Experience:Digital design verificationSoC/CPU/GPUASICDFT/DFxHardware emulation
Education:
Skills:CommunicationTeamworkAnalytical skillsProblem-solvingCollaborationWillingness to learn
Languages:En-us
Tech Stack:SystemVerilogUVMDFxScanATPGTest compressionLBISTMBISTJTAGIEEE 1149.xBoundary scanSystemVerilog DPIC/C++PythonPerlTclShellBFMAgentsMonitors

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
WebsiteLinkedIn