Hardware - Silicon Validation Engineer (NPU SoC)

FuriosaAI
Seoul
Workplace: OnsiteFull timeFunction: Healthcare (Clinical, Medical, Wellness)Skills: ["Problem-solving","Debugging","Logical analysis","Persistence","Cross-functional collaboration"]

Own system-level validation for NPU SoCs from 1st silicon bring-up through performance optimization and stability. Bridge RTL/DV design and firmware/OS, developing test plans and bare-metal test firmware across pre- and post-silicon environments. Debug complex HW/SW co-issues (e.g., via JTAG/Trace32), derive workarounds, and support high-speed interface and memory subsystem bring-up while improving validation efficiency through test automation and CI/CD integration.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
FuriosaAI
FuriosaAI
2 weeks ago

Hardware - Silicon Validation Engineer (NPU SoC)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 1 hour agoStatus: Live

Job Summary

Own system-level validation for NPU SoCs from 1st silicon bring-up through performance optimization and stability. Bridge RTL/DV design and firmware/OS, developing test plans and bare-metal test firmware across pre- and post-silicon environments. Debug complex HW/SW co-issues (e.g., via JTAG/Trace32), derive workarounds, and support high-speed interface and memory subsystem bring-up while improving validation efficiency through test automation and CI/CD integration.
Location: Seoul
Workplace: Onsite
Employment Type: Full time
Job Function: Healthcare (Clinical, Medical, Wellness)

Key Responsibilities

  • •Lead NPU 1st-silicon bring-up by validating core accelerators, CPU subsystem, NoC, and initial system boot/bring-up (booting sequence, clock/reset).
  • •Define and execute validation methodology, including pre- and post-silicon test planning, coverage management, and developing test firmware and scenarios.
  • •Perform system-level issue debugging across HW/RLT and SW/firmware-driver boundaries using JTAG/trace tools and produce workaround solutions.
  • •Support performance validation and optimization by validating NPU data pipelines and memory bandwidth.
  • •Improve validation efficiency with test automation scripts and CI/CD integration for validation environments.

Key Requirements

  • •Experience with SoC/ASIC or complex silicon/system validation (leader-level reading/leading experience required for leader roles).
  • •Strong understanding of ARM architecture and AMBA bus (AXI, AHB) plus overall SoC/computer architecture.
  • •Ability to program hardware control and IP tests using Embedded C/C++ and Rust in bare-metal environments.
  • •Experience with validation methodology end-to-end, from test plan creation and bug tracking to coverage.
  • •Expert debugging skills using JTAG debuggers (e.g., Trace32) and strong HW/SW co-debugging capability.
Experience:SoCASICSilicon validationSystem validationNPU
Skills:Problem-solvingDebuggingLogical analysisPersistenceCross-functional collaboration
Languages:English
Tech Stack:NPUSoCASICRTLDVFirmwareOSLPDDRHBMEthernetNoCJTAGTrace32Embedded CC++RustBare-metalTest PlanEmulatorFPGA

Company Brief

FuriosaAI
Designs and develops data‑center AI inference accelerators (RNGD) and a full stack hardware‑software platform to deliver energy‑efficient, high‑performance AI compute for enterprise and cloud customers.
Industry: Hardware Devices
Company Size: Medium (51 to 250 employees)
Growth: Scaleup
Valuation: USD 500M to 1B
Funding: Series C
Headquarters: Seoul, South Korea
Founded: 2017
Glassdoor
Glassdoor: 4.6
WebsiteLinkedInGlassdoor