Synthesis & STA Engineer -Singapore

Own logic synthesis and timing closure for chip architectures and RTLs, including SDC preparation, hierarchical/full-chip STA signoff, and power-aware constraint tuning. Implement low-power techniques using UPF, clock/power gating, and dynamic voltage scaling, while partnering with front-end and backend teams on architectural exploration and floorplanning/P&R. Drive formal verification and equivalence checking with tools such as Conformal and Formality.