Physical Design Engineer

AMD
Karnataka, India
Full timeINR 2,186,520 - 3,123,600 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 2-6 yearsEducation: mastersSkills: ["Debugging","Problem-solving","Cross-functional collaboration"]

Own and drive clocking and Physical Design (PnR) methodologies for complex SoC/ASIC designs. Develop, validate, and maintain implementation flows including CTS architecture, clock QoR reviews, timing correlation, and QoR convergence strategies. Define recipes for timing, congestion, power, and area closure; build automation using Tcl/Python/Shell; and partner across CAD, timing, DFT, and design teams to enable new technology nodes and improve project execution.

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FursaFursa
AMD
AMD
6 days ago

Physical Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 7 hours agoStatus: Live

Job Summary

Own and drive clocking and Physical Design (PnR) methodologies for complex SoC/ASIC designs. Develop, validate, and maintain implementation flows including CTS architecture, clock QoR reviews, timing correlation, and QoR convergence strategies. Define recipes for timing, congestion, power, and area closure; build automation using Tcl/Python/Shell; and partner across CAD, timing, DFT, and design teams to enable new technology nodes and improve project execution.
Location: Karnataka, India
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Own end-to-end clocking methodology including CTS architecture, clock latency/skew management, clock QoR reviews, and timing convergence strategies.
  • •Develop, certify, and maintain PnR implementation flows across technology nodes and design styles.
  • •Drive flow correlation between Tile PnR, Full-Chip Timing (FCT), STA, and signoff environments to ensure predictable closure.
  • •Define implementation recipes and optimisation strategies for timing, congestion, power, and area closure.
  • •Develop automation using Tcl/Python/Shell and partner with CAD, FCFP, Timing, DFT, and Design teams to resolve methodology issues.

Pay and Benefits

Salary: INR 2,186,520 - 3,123,600 annually

Key Requirements

  • •Bachelor's/Master's degree in Electrical/Electronics Engineering.
  • •Strong understanding of ASIC Physical Design flow including Floorplanning, Placement, CTS, Routing, STA, ECO, IR/EM, and Physical Verification.
  • •Expertise in clock-tree synthesis, clock skew/latency optimisation, and timing closure methodologies.
  • •Experience with industry-standard tools such as Fusion Compiler, ICC2, Innovus, PrimeTime, Calibre, and RedHawk.
  • •Strong scripting skills in Tcl, Python, and Shell.
Experience:2-6 years
Education:Master's in Electrical/Electronics Engineering
Skills:DebuggingProblem-solvingCross-functional collaboration
Tech Stack:TclPythonShellFusion CompilerICC2InnovusPrimeTimeCalibreRedHawk

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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