ASIC Physical Design Engineer, Netlisting - New College Grad 2026

NVIDIA
Santa Clara, Austin
Workplace: OnsiteFull timeUSD 116,000 - 218,500Function: Design (Product/UX/UI/Visual)Education: mastersSkills: ["RTL","Timing closure","Logic synthesis","Netlist","EVA","Equivalence checking","MTBF","Scripting","Python","Perl","TCL","Make"]

ASIC Physical Design Engineer specializing in netlisting and timing-focused hardware design for CPUs/GPUs/SoCs. Role emphasizes RTL/Formal Verification, clock-domain crossing, MTBF analysis, and ECO generation, with hands-on EDA tool usage and scripting to improve design workflows in a fast-paced AI computing environment.

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FursaFursa
NVIDIA
NVIDIA
2 months ago

ASIC Physical Design Engineer, Netlisting - New College Grad 2026

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 5 hours agoStatus: Live

Job Summary

ASIC Physical Design Engineer specializing in netlisting and timing-focused hardware design for CPUs/GPUs/SoCs. Role emphasizes RTL/Formal Verification, clock-domain crossing, MTBF analysis, and ECO generation, with hands-on EDA tool usage and scripting to improve design workflows in a fast-paced AI computing environment.
Location: Santa Clara, Austin
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Entry level

Key Responsibilities

  • •Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block/cluster/full chip level with a focus on netlist-related aspects (equivalence checking, clock-domain crossing checks, MTBF analysis) and timing closure
  • •Perform logic synthesis and netlist quality checks to ensure design correctness and performance
  • •Contribute to ECO generation and implementation
  • •Engage in debugging and problem-solving to improve design flows and verify timing closure
  • •Collaborate with cross-functional teams to implement and verify design methodologies and tool flows

Pay and Benefits

Salary: USD 116,000 - 218,500
Equity and Bonus:Equity

Key Requirements

  • •Master's or PhD degree in Electrical or Computer Engineering (or equivalent experience)
  • •Knowledge in logic equivalence checking/Formal Verification required from RTL to tapeout with industry-standard tools
  • •Understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure
  • •Experience in clock-domain-crossing checking, MTBF analysis using EDA tools (e.g., Synopsys or Cadence) or in-house tools
  • •Background with logic synthesis at block or full-chip level, project execution and/or flow development
Experience:SemiconductorHardwareEDA
Education:Master's
Skills:RTLTiming closureLogic synthesisNetlistEVAEquivalence checkingMTBFScriptingPythonPerlTCLMake
Languages:English
Tech Stack:PerlTCLMakePythonSynopsysCadenceRTLTiming closureEDA tooling

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
Glassdoor
Glassdoor: 4.3
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