Silicon Design Engineer

AMD
Shanghai
Workplace: OnsiteFull timeCNY 556,850 - 795,500 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: mastersSkills: ["Detail-oriented","Communication","Problem-solving","Collaboration","Drive to completion","Execution leadership"]

Lead IOHUB Subsystem verification strategy and scoping for AMD’s NBIO team, defining and driving the subsystem test plan through driver implementation and verification closure. Partner closely with design/architecture teams to build new verification components, align on status and strategy with a global group, and support short-term global travel as needed. This role focuses on complex ASIC/SOC and IP verification using coverage-based methods and assertions.

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FursaFursa
AMD
AMD
14 hours ago

Silicon Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 2 hours agoStatus: Live

Job Summary

Lead IOHUB Subsystem verification strategy and scoping for AMD’s NBIO team, defining and driving the subsystem test plan through driver implementation and verification closure. Partner closely with design/architecture teams to build new verification components, align on status and strategy with a global group, and support short-term global travel as needed. This role focuses on complex ASIC/SOC and IP verification using coverage-based methods and assertions.
Location: Shanghai
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Own IOHUB Subsystem verification strategy and scoping activities.
  • •Create and drive the IOHUB Subsystem test plan, including driver implementation and verification closure.
  • •Collaborate with Design/Architecture to develop new verification components.
  • •Coordinate with global teams through conference calls for strategy alignment and status updates.
  • •Support short-term global travel if needed.
Travel: Low travel

Pay and Benefits

Salary: CNY 556,850 - 795,500 annually

Key Requirements

  • •Drive IOHUB Subsystem verification strategy and scoping, including test plan creation and verification closure.
  • •Good knowledge of UVM and hardware verification flows using Verilog/SystemVerilog and/or SystemC.
  • •Solid verification background with coverage-based verification and hardware assertions (PSL or SVA), plus experience with random techniques.
  • •Preferred experience with complex IP/ASIC/SOC design verification and direct experience with IP/SOC, processors (CPU/GPU), or industry bus standards (PCIe, HT).
  • •MSEE (8+ years) or BSEE (9+ years) in digital ASIC/SOC design verification.
Experience:8+ yearsASICSOCIP verificationHardware verification
Education:Master's
Skills:Detail-orientedCommunicationProblem-solvingCollaborationDrive to completionExecution leadership
Languages:EnglishVerbal English
Tech Stack:UVMVerilogSystem CSystem VerilogPSLSVACoverage-based verificationRandom techniquesPerlC ShellMakefilePCIeVirtualizationIO virtualizationIOMMUIOHub CoreIOHUB Subsystem

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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