Design Verification Engineer, Coherent Interconnect

Samsung
Austin, San Jose
Workplace: OnsiteFull time151,000 - 251,800 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 10+ yearsEducation: bachelorsSkills: ["SystemVerilog","UVM","Git","Unix","Perl","ARM protocols (CHI, AXI, ACElite, APB)","LPDDR","Memory controllers","Testbenches"]

Design Verification Engineer responsible for verifying System IP including coherent interconnects and caches. Develops verification environments/testbenches from scratch, applies SystemVerilog/UVM, collaborates across design/SoC teams, and contributes to verification methodologies for high-performance, low-latency interconnects powering next-generation Exynos/SOC designs.

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FursaFursa
Samsung
Samsung
5 months ago

Design Verification Engineer, Coherent Interconnect

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Source: Company careers pageValidated by: Fursa AI
Last checked: 11 hours agoStatus: Live

Job Summary

Design Verification Engineer responsible for verifying System IP including coherent interconnects and caches. Develops verification environments/testbenches from scratch, applies SystemVerilog/UVM, collaborates across design/SoC teams, and contributes to verification methodologies for high-performance, low-latency interconnects powering next-generation Exynos/SOC designs.
Location: Austin, San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Develop and maintain deep expertise in microarchitecture and design verification for coherent interconnect IPs to develop, verify, and optimize high-performance, low-latency interconnect solutions for complex SoCs.
  • •Architect, develop, and maintain reusable verification environments and testbenches from scratch, including stimulus, assertions, checkers, covergroups, and SystemVerilog constraints.
  • •Support design excellence and thorough verification by contributing to test plans, verifying feature correctness, debugging regressions, and performing coverage analysis to identify gaps.
  • •Contribute to verification methodologies, improve flows, and adopt practices such as power-aware verification with UPF and gate-level simulations.
  • •Collaborate with design, SoC, physical design, and performance verification teams to debug failures, resolve spec issues, and enable bring-up across IP, SoC, and silicon.

Pay and Benefits

Salary: 151,000 - 251,800 annually
Perks:MedicalDentalVision401kTuition AssistanceWellness StipendRelocation

Key Requirements

  • •10+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 8+ years with a Master’s Degree, or 6+ years with a Ph.D.
  • •8+ years of professional experience in a design verification role building testbenches from scratch
  • •Strong background in design verification of coherent interconnects; LPDDR memory controller experience a plus
  • •Proficiency in SystemVerilog, UVM
  • •Experience with Git version control, Unix/Perl scripting
Experience:10+ yearsSemiconductorIPSoCCoherent interconnect
Education:Bachelor's
Skills:SystemVerilogUVMGitUnixPerlARM protocols (CHI, AXI, ACElite, APB)LPDDRMemory controllersTestbenches
Tech Stack:SystemVerilogUVMGitUnixPerlARM CHIARM AXIACEliteAPBLPDDR

Company Brief

Samsung
Global conglomerate known for consumer electronics, home appliances, semiconductors, displays, and mobile devices. Designs and manufactures a wide range of products and solutions for consumers, enterprises, and industrial customers worldwide.
Industry: Conglomerates & Holding Companies
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Seoul, South Korea
Founded: 1938
Glassdoor
Glassdoor: 3.7
WebsiteLinkedIn