Principal/Staff/Senior Engineer, APTD CEM - Advanced Packaging Wafer Level Technology Engineering
Singapore
Workplace: OnsiteFull timeFunction: Solutions Engineering & Sales EngineeringExperience: 2+ yearsEducation: phdSkills: ["Collaboration","Problem-solving","Data analysis","Tenacity"]Develop and improve wafer-level semiconductor post-fab finishing processes for high-performance memory, focusing on performance, cost, manufacturability, quality, reliability, and schedule. Establish wafer thinning and backside metal interconnect process conditions, evaluate equipment/materials, and drive quality improvements via correlations, inspection/testing, and advanced controls. Partner across packaging and engineering teams to integrate and transition technologies from development through high-volume manufacturing, including POR/MOR documentation.
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