Design Verification Engineer - Internal IP

Etched
Austin
Workplace: OnsiteFull timeUSD 150,000 - 275,000 annuallyFunction: Design (Product/UX/UI/Visual)Skills: ["Communication","Problem-solving","Collaboration","Attention to detail"]

Design Verification Engineer to join Etched's Internal IP DV team, ensuring custom IPs powering Sohu (systolic arrays, DMAs, NoCs) are robust, high-performance, and silicon-ready. Collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the hardware-software stack, developing UVM/SystemVerilog testbenches and reusable DV infrastructure from Austin with time in San Jose.

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FursaFursa
Etched
Etched
5 months ago

Design Verification Engineer - Internal IP

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Source: Company careers pageValidated by: Fursa AI
Last checked: 6 hours agoStatus: Live

Job Summary

Design Verification Engineer to join Etched's Internal IP DV team, ensuring custom IPs powering Sohu (systolic arrays, DMAs, NoCs) are robust, high-performance, and silicon-ready. Collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the hardware-software stack, developing UVM/SystemVerilog testbenches and reusable DV infrastructure from Austin with time in San Jose.
Location: Austin
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems).
  • •Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks.
  • •Debug complex datapath and protocol issues in RTL and testbench environments.
  • •Work closely with architects and designers to validate functionality and design intent.
  • •Partner with SW, FW, and emulation teams to ensure end-to-end bring-up and debug coverage.

Pay and Benefits

Salary: USD 150,000 - 275,000 annually
Equity and Bonus:Equity
Perks:Health InsuranceVisionDentalHousing SubsidyRelocationMeal Allowance

Key Requirements

  • •Proficiency with UVM and SystemVerilog.
  • •Strong debugging and problem-solving skills for complex digital designs.
  • •Solid knowledge of computer architecture and digital design fundamentals.
  • •Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics.
  • •Scripting skills (Python/Perl/TCL or similar) for automation, debug and regression flows.
Experience:SemiconductorsHardwareAI hardwareASIC
Skills:CommunicationProblem-solvingCollaborationAttention to detail
Languages:English
Tech Stack:UVMSystemVerilogSystemVerilog AssertionsPythonPerlTCLNoCsDMAAXISVARAMMemory subsystems

Company Brief

Etched
Designs transformer‑specialized AI inference ASICs (product: Sohu) to accelerate large‑language‑model workloads, working with TSMC for fabrication and targeting energy‑efficient inference performance.
Industry: Hardware Devices
Company Size: Medium (51 to 250 employees)
Growth: Early Stage Startup
Valuation: Unicorn (USD 1B+)
Funding: Series A
Headquarters: San Jose, United States
Founded: 2022
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