Principal Software Engineer

Cadence Design Systems
Noida
Workplace: OnsiteFull timeFunction: Software EngineeringExperience: 5-10 yearsEducation: bachelorsSkills: ["Verilog","SystemVerilog","UVM","C++","Python","Shell scripting","Cadence Xcelium","DFT","ATPG"]

Lead the design and verification of pre-silicon IP to top digital integration, developing flexible UVM-based verification environments, writing test plans, and automating regression with modern EDA tools. You’ll define verification strategy, build test benches, and drive coverage and bug-resolution across SoCs, IPs, and block-level architectures in a large hardware/software ecosystem.

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FursaFursa
Cadence Design Systems
Cadence Design Systems
3 years ago

Principal Software Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 19 hours agoStatus: Live

Job Summary

Lead the design and verification of pre-silicon IP to top digital integration, developing flexible UVM-based verification environments, writing test plans, and automating regression with modern EDA tools. You’ll define verification strategy, build test benches, and drive coverage and bug-resolution across SoCs, IPs, and block-level architectures in a large hardware/software ecosystem.
Location: Noida
Workplace: Onsite
Employment Type: Full time
Job Function: Software Engineering
Seniority: Sr. Manager level

Key Responsibilities

  • •Design and implement a full, dedicated, and flexible (e.g., UVM based) verification environment
  • •Define verification strategy from IP to top digital integration
  • •Create test plans for unit-level and chip-level verification and post-silicon validation
  • •Debug failures and drive in-time resolution of bugs
  • •Develop tools, test benches, and test suites (UVM, C/C++) to execute test plans

Key Requirements

  • •BS or MS in EE/CS or related engineering discipline with 5-10 years verification experience of IPs, Digital Design and SoCs
  • •Strong experience with design and verification standards and methodologies (SVA, UVM/OVM)
  • •In-depth knowledge of Verilog and SystemVerilog HDL with simulators and waveform debugging tools
  • •Solid understanding of verification of Digital Design and SoC architectures including test planning, constrained random test generation, test stimulus, code and functional coverage
  • •Programming experience in C, C++, Shell scripting; scripting with Python (preferred)
Experience:5-10 yearsSemiconductorsSoCsVerificationDigital design
Education:Bachelor's in Electrical Engineering / Computer Science
Skills:VerilogSystemVerilogUVMC++PythonShell scriptingCadence XceliumDFTATPG
Tech Stack:VerilogSystemVerilogUVMC++PythonShellCadence XceliumATPGDFT

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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