ASIC Physical Design Technical Lead

Lead the RTL-to-GDSII physical design flow for ASICs, owning fullchip floorplanning, power integrity, and timing closure while collaborating with RTL, DFT, and EDA teams. Drive hierarchical implementation, clock planning, and signoff methodologies with a focus on performance, power, and die size optimization in a fast-paced CHG environment powering Cisco’s AI-era hardware platforms.