Lead Design Verification Engineer-Memory Controller

AMD
San Jose
Workplace: OnsiteFull timeUSD 175,000 - 300,000 annuallyFunction: Finance & AccountingExperience: 8+ yearsSkills: ["Leadership","Communication","Mentoring","Teamwork","Technical leadership"]

Lead verification for cutting-edge DRAM Memory Controller IPs (DDR5, LPDDR6, HBM4), high-speed Crypto, and Network-on-Chip designs. Architect and build simulation and/or formal verification environments for both IP blocks and SoCs, owning verification planning, testbenches, and closure. Manage verification execution for multi-engineer teams, partner with design/architecture/software to define strategy, and use UVM, formal verification, and assertion-based methods to drive first-pass silicon success.

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FursaFursa
AMD
AMD
22 hours ago

Lead Design Verification Engineer-Memory Controller

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Source: Company careers pageValidated by: Fursa AI
Last checked: 9 hours agoStatus: Live

Job Summary

Lead verification for cutting-edge DRAM Memory Controller IPs (DDR5, LPDDR6, HBM4), high-speed Crypto, and Network-on-Chip designs. Architect and build simulation and/or formal verification environments for both IP blocks and SoCs, owning verification planning, testbenches, and closure. Manage verification execution for multi-engineer teams, partner with design/architecture/software to define strategy, and use UVM, formal verification, and assertion-based methods to drive first-pass silicon success.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Finance & Accounting
Seniority: Manager level

Key Responsibilities

  • •Lead verification of high-speed Crypto, Network-on-Chip (NoC), and cutting-edge DRAM memory controller designs (DDR5, LPDDR6, HBM4) to ensure quality and performance.
  • •Architect, develop, and use simulation and/or formal verification environments at both IP and SoC level.
  • •Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs.
  • •Develop and execute comprehensive verification plans, including testbenches and test cases.
  • •Collaborate with design, architecture, and software teams to define and implement verification strategies; mentor junior engineers.

Pay and Benefits

Salary: USD 175,000 - 300,000 annually

Key Requirements

  • •Experience driving pre-silicon verification strategies for Design IP and/or SoC designs, including verification planning and closure.
  • •Hands-on verification experience with state-of-the-art memory controllers such as DDR, LPDDR, and HBM, including protocol understanding and calibration (DDR3/4/5, LPDDR4/5/6, HBM2/3/4).
  • •Technical leadership experience managing verification teams (5+ engineers) across planning, execution, tracking, closure, and program delivery.
  • •Hands-on development of UVM and SystemVerilog testbenches, with simulation/debug tool experience using Synopsys VCS or Cadence Xcelium.
  • •Strong verification methodology knowledge, including assertion-based and metric-driven verification; familiarity with verification management and regression database management.
Experience:8+ yearsDRAMSoCPre-siliconVerificationVLSI
Education:
Skills:LeadershipCommunicationMentoringTeamworkTechnical leadership
Languages:En-us
Tech Stack:UVMSystemVerilogSynopsys VCSCadence XceliumVC FormalJasperGoldQuesta Formal

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
WebsiteLinkedIn